Lines Matching +full:pin +full:- +full:switches

2 spi_lm70llp :  LM70-LLP parport-to-SPI adapter
15 -----------
27 --------------------
28 The schematic for this particular board (the LM70EVAL-LLP) is
39       D0     2      -         -
40       D1     3     -->      V+   5
41       D2     4     -->      V+   5
42       D3     5     -->      V+   5
43       D4     6     -->      V+   5
44       D5     7     -->      nCS  8
45       D6     8     -->      SCLK 3
46       D7     9     -->      SI/O 5
47      GND    25      -       GND  7
48     Select  13     <--      SI/O 1
51 Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
52 is connected to both pin D7 (as Master Out) and Select (as Master In)
54 pin low.  This can't be shared with true SPI devices, but other 3-wire
55 devices might share the same SI/SO pin.
69 and not grounded by the host via D7), the transistor conducts and switches
70 the collector to zero, which is reflected on pin 13 of the DB25 parport
73 reflected on pin 13 as a High level.
76 inverting the value read at pin 13.
80 ---------
82 - David Brownell for mentoring the SPI-side driver development.
83 - Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
84 - Nadir Billimoria for help interpreting the circuit schematic.