Lines Matching +full:tpm +full:- +full:tis +full:- +full:mmio

1 .. SPDX-License-Identifier: GPL-2.0
4 TPM FIFO interface driver
11 FIFO (First-In-First-Out) interface is used by the tpm_tis_core dependent
13 memory mapped (aka MMIO) interface but it was later on extended to cover other
16 For historical reasons above the original MMIO driver is called tpm_tis and the
17 framework for FIFO drivers is named as tpm_tis_core. The postfix "tis" in
18 tpm_tis comes from the TPM Interface Specification, which is the hardware
19 interface specification for TPM 1.x chips.
21 Communication is based on a 20 KiB buffer shared by the TPM chip through a
23 further split into five equal-size 4 KiB buffers, which provide equivalent
24 sets of registers for communication between the CPU and TPM. These
27 When the kernel wants to send commands to the TPM chip, it first reserves
36 - Locality 0 has the lowest priority.
37 - Locality 5 has the highest priority.
40 in section 3.2 of the TCG PC Client Platform TPM Profile Specification.
45 TCG PC Client Platform TPM Profile (PTP) Specification
46 https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/