Lines Matching +full:machine +full:- +full:mode
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
114 MAC driver looks at the phy_interface_t value, for any other mode but
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
192 PHY's software state machine, and registered for the PHY's interrupt, if it
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
205 RGMII, and SGMII. See "PHY interface mode" below. For a full
208 Now just make sure that phydev->supported and phydev->advertising have any
219 also handles PHY status changes, just set phydev->irq to PHY_MAC_INTERRUPT
221 driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL.
223 phylib state machine.
226 phy_stop(phydev). This function also stops the phylib state machine and
232 The PHY interface mode supplied in the phy_connect() family of functions
233 defines the initial operating mode of the PHY interface. This is not
235 their interface mode without software interaction depending on the
246 This defines the 1000BASE-X single-lane serdes link as defined by the
249 data rate of 1Gbps. Embedded in the data stream is a 16-bit control
251 remote end. This does not include "up-clocked" variants such as 2.5Gbps
255 This defines a variant of 1000BASE-X which is clocked 2.5 times as fast
259 This is used for Cisco SGMII, which is a modification of 1000BASE-X
264 The 802.3 control word is re-purposed to send the negotiated speed and
266 receipt. This does not include "up-clocked" variants such as 2.5Gbps
269 Note: mismatched SGMII vs 1000BASE-X configuration on a link can
270 successfully pass data in some circumstances, but the 16-bit control
276 This is the IEEE 802.3 Clause 129 defined 5GBASE-R protocol. It is
277 identical to the 10GBASE-R protocol defined in Clause 49, with the
282 This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used with
286 Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.
293 This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73
297 Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
301 This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
302 The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
312 This defines the Cisco the Quad USGMII mode, which is the Quad variant of
315 only the port id, but also so-called "extensions". The only documented
316 extension so-far in the specification is the inclusion of timestamps, for
317 PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
321 This is 1000BASE-X as defined by IEEE 802.3 Clause 36 with Clause 73
323 contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
324 interface mode has different autonegotiation and only supports full duplex.
327 This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
331 Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
337 Non-standard, simplified MII mode, without TXER, RXER, CRS and COL signals
338 as defined for the MII. The absence of COL signal makes half-duplex link
339 modes impossible but does not interfere with BroadR-Reach link modes on
340 Broadcom (and other two-wire Ethernet) PHYs, because they are full-duplex
360 It is possible that the PAL's built-in state machine needs a little help to
363 every second before the state machine reacts to any changes. To do this, you
375 There's a remote chance that the PAL's built-in state machine cannot track
378 phy_prepare_link(). This will mean that phydev->state is entirely yours to
383 accessed without the state-machine running, and most of these functions are
384 descended from functions which did not interact with a complex state-machine.
386 state machine, so tryer beware.
423 Fills the phydev structure with up-to-date information about the current
437 machine if you write registers like BMCR, BMSR, ADVERTISE, etc. Best to
446 many PHYs require a little hand-holding to get up-and-running.
449 ------------------
457 --------------------
519 field) and the bus identifier (contained in phydev->dev.bus_id). Both must
558 http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf