Lines Matching +full:10 +full:gbase +full:- +full:r
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
144 * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
208 Now just make sure that phydev->supported and phydev->advertising have any
209 values pruned from them which don't make sense for your controller (a 10/100
219 also handles PHY status changes, just set phydev->irq to PHY_MAC_INTERRUPT
221 driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL.
241 This is serial MII, clocked at 125MHz, supporting 100M and 10M speeds.
246 This defines the 1000BASE-X single-lane serdes link as defined by the
248 1.25Gbaud using a 10B/8B encoding scheme, resulting in an underlying
249 data rate of 1Gbps. Embedded in the data stream is a 16-bit control
251 remote end. This does not include "up-clocked" variants such as 2.5Gbps
255 This defines a variant of 1000BASE-X which is clocked 2.5 times as fast
259 This is used for Cisco SGMII, which is a modification of 1000BASE-X
261 serdes lane running at a fixed bit rate of 1.25Gbaud with 10B/8B
263 100Mbps and 10Mbps being achieved through replication of each data symbol.
264 The 802.3 control word is re-purposed to send the negotiated speed and
266 receipt. This does not include "up-clocked" variants such as 2.5Gbps
269 Note: mismatched SGMII vs 1000BASE-X configuration on a link can
270 successfully pass data in some circumstances, but the 16-bit control
276 This is the IEEE 802.3 Clause 129 defined 5GBASE-R protocol. It is
277 identical to the 10GBASE-R protocol defined in Clause 49, with the
282 This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used with
286 Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.
293 This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73
297 Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
301 This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
302 The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
315 only the port id, but also so-called "extensions". The only documented
316 extension so-far in the specification is the inclusion of timestamps, for
317 PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
321 This is 1000BASE-X as defined by IEEE 802.3 Clause 36 with Clause 73
323 contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
331 Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
333 SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
353 It is possible that the PAL's built-in state machine needs a little help to
368 There's a remote chance that the PAL's built-in state machine cannot track
371 phy_prepare_link(). This will mean that phydev->state is entirely yours to
376 accessed without the state-machine running, and most of these functions are
377 descended from functions which did not interact with a complex state-machine.
416 Fills the phydev structure with up-to-date information about the current
439 many PHYs require a little hand-holding to get up-and-running.
442 ------------------
450 --------------------
512 field) and the bus identifier (contained in phydev->dev.bus_id). Both must
551 http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf