Lines Matching refs:CPU

8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
39  CPU-thread-0  {try to write to addrA}
40  CPU-thread-1  {try to write to addrB}
41  CPU-thread-2  {}
42  CPU-thread-3  {}
46  CPU-thread-0  {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
47  CPU-thread-1  {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
48  CPU-thread-2  {}
49  CPU-thread-3  {}
53  CPU-thread-0  {COW_step1: {update page table to point to new page for addrA}}
54  CPU-thread-1  {COW_step1: {update page table to point to new page for addrB}}
55  CPU-thread-2  {}
56  CPU-thread-3  {}
60  CPU-thread-0  {preempted}
61  CPU-thread-1  {preempted}
62  CPU-thread-2  {write to addrA which is a write to new page}
63  CPU-thread-3  {}
67  CPU-thread-0  {preempted}
68  CPU-thread-1  {preempted}
69  CPU-thread-2  {}
70  CPU-thread-3  {write to addrB which is a write to new page}
74  CPU-thread-0  {preempted}
75  CPU-thread-1  {COW_step3: {mmu_notifier_invalidate_range_end(addrB)}}
76  CPU-thread-2  {}
77  CPU-thread-3  {}
81  CPU-thread-0  {preempted}
82  CPU-thread-1  {}
83  CPU-thread-2  {}
84  CPU-thread-3  {}