Lines Matching +full:memory +full:- +full:to +full:- +full:memory
2 Heterogeneous Memory Management (HMM)
5 Provide infrastructure and helpers to integrate non-conventional memory (device
6 memory like GPU on board memory) into regular kernel path, with the cornerstone
7 of this being specialized struct page for such memory (see sections 5 to 7 of
10 HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
11 allowing a device to transparently access program addresses coherently with
13 for the device. This is becoming mandatory to simplify the use of advanced
14 heterogeneous computing where GPU, DSP, or FPGA are used to perform various
18 related to using device specific memory allocators. In the second section, I
19 expose the hardware limitations that are inherent to many platforms. The third
21 CPU page-table mirroring works and the purpose of HMM in this context. The
22 fifth section deals with how device memory is represented inside the kernel.
28 Problems of using a device specific memory allocator
31 Devices with a large amount of on board memory (several gigabytes) like GPUs
32 have historically managed their memory through dedicated driver specific APIs.
33 This creates a disconnect between memory allocated and managed by a device
34 driver and regular application memory (private anonymous, shared memory, or
35 regular file backed memory). From here on I will refer to this aspect as split
36 address space. I use shared address space to refer to the opposite situation:
37 i.e., one in which any application memory region can be used by a device
40 Split address space happens because devices can only access memory allocated
41 through a device specific API. This implies that all memory objects in a program
45 Concretely, this means that code that wants to leverage devices like GPUs needs
46 to copy objects between generically allocated memory (malloc, mmap private, mmap
47 share) and memory allocated through the device driver API (this still ends up
50 For flat data sets (array, grid, image, ...) this isn't too hard to achieve but
51 for complex data sets (list, tree, ...) it's hard to get right. Duplicating a
52 complex data set needs to re-map all the pointer relations between each of its
53 elements. This is error prone and programs get harder to debug because of the
58 might have to duplicate its input data set using the device specific memory
60 various memory copies.
62 Duplicating each library API to accept as input or output memory allocated by
63 each device specific allocator is not a viable option. It would lead to a
67 other languages too) it is now possible for the compiler to leverage GPUs and
69 are only doable with a shared address space. It is also more reasonable to use
73 I/O bus, device memory characteristics
76 I/O buses cripple shared address spaces due to a few limitations. Most I/O
77 buses only allow basic memory access from device to main memory; even cache
78 coherency is often optional. Access to device memory from a CPU is even more
81 If we only consider the PCIE bus, then a device can access main memory (often
83 a limited set of atomic operations from the device on main memory. This is worse
85 memory and cannot perform atomic operations on it. Thus device memory cannot
86 be considered the same as regular memory from the kernel point of view.
89 and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
90 The final limitation is latency. Access to main memory from the device has an
91 order of magnitude higher latency than when the device accesses its own memory.
93 Some platforms are developing new I/O buses or additions/modifications to PCIE
94 to address some of these limitations (OpenCAPI, CCIX). They mainly allow
95 two-way cache coherency between CPU and device and allow all atomic operations the
97 some major architectures are left without hardware solutions to these problems.
99 So for shared address space to make sense, not only must we allow devices to
100 access any memory but we must also permit any memory to be migrated to device
101 memory while the device is using it (blocking CPU access while it happens).
107 HMM intends to provide two main features. The first one is to share the address
109 address points to the same physical memory for any valid main memory address in
112 To achieve this, HMM offers a set of helpers to populate the device page table
114 not as easy as CPU page table updates. To update the device page table, you must
115 allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
116 specific commands in it to perform the update (unmap, cache invalidations, and
118 why HMM provides helpers to factor out everything that can be while leaving the
119 hardware specific details to the device driver.
121 The second mechanism HMM provides is a new kind of ZONE_DEVICE memory that
122 allows allocating a struct page for each page of device memory. Those pages
124 main memory to device memory using existing migration mechanisms and everything
125 looks like a page that is swapped out to disk from the CPU point of view. Using a
127 mechanisms. Here again, HMM only provides helpers, first to hotplug new ZONE_DEVICE
128 memory for the device memory and second to perform migration. Policy decisions
129 of what and when to migrate is left to the device driver.
131 Note that any CPU access to a device page triggers a page fault and a migration
132 back to main memory. For example, when a page backing a given CPU address A is
133 migrated from a main memory page to a device page, then any CPU access to
134 address A triggers a page fault and initiates a migration back to main memory.
136 With these two features, HMM not only allows a device to mirror process address
138 leverages device memory by migrating the part of the data set that is actively being
145 Address space mirroring's main objective is to allow duplication of a range of
147 device driver that wants to mirror a process address space must start with the
155 During the ops->invalidate() callback the device driver must perform the
156 update action to the range (mark range read only, or fully unmap, etc.). The
159 When the device driver wants to populate a range of virtual addresses, it can
164 It will trigger a page fault on missing or read-only entries if write access is
178 if (!mmget_not_zero(interval_sub->notifier.mm))
179 return -EFAULT;
187 if (ret == -EBUSY)
193 take_lock(driver->update);
195 release_lock(driver->update);
199 /* Use pfns array content to update device page table,
202 release_lock(driver->update);
206 The driver->update lock is the same lock that the driver takes inside its
208 mmu_interval_read_retry() to avoid any race with a concurrent CPU page table
215 fault or snapshot policy for the whole range instead of having to set them
221 range->default_flags = HMM_PFN_REQ_FAULT;
222 range->pfn_flags_mask = 0;
227 Now let's say the driver wants to do the same except for one page in the range for
228 which it wants to have write permission. Now driver set::
230 range->default_flags = HMM_PFN_REQ_FAULT;
231 range->pfn_flags_mask = HMM_PFN_REQ_WRITE;
232 range->pfns[index_of_write] = HMM_PFN_REQ_WRITE;
235 address == range->start + (index_of_write << PAGE_SHIFT) it will fault with
239 After hmm_range_fault completes the flag bits are set to the current state of
244 Represent and manage device memory from core kernel point of view
247 Several different designs were tried to support device memory. The first one
248 used a device specific data structure to keep information about migrated memory
249 and HMM hooked itself in various places of mm code to handle any access to
250 addresses that were backed by device memory. It turns out that this ended up
252 paths to be updated to understand this new kind of memory.
254 Most kernel code paths never try to access the memory behind a page
255 but only care about struct page contents. Because of this, HMM switched to
256 directly using struct page for device memory which left most kernel code paths
257 unaware of the difference. We only need to make sure that no one ever tries to
260 Migration to and from device memory
263 Because the CPU cannot access device memory directly, the device driver must
264 use hardware DMA or device specific load/store instructions to migrate data.
266 functions are designed to make drivers easier to write and to centralize common
269 Before migrating pages to device private memory, special device private
270 ``struct page`` needs to be created. These will be used as special "swap"
271 page table entries so that a CPU process will fault if it tries to access
272 a page that has been migrated to device private memory.
282 pagemap.range.start = res->start;
283 pagemap.range.end = res->end;
293 be tied to a ``struct device``.
295 The overall migration steps are similar to migrating NUMA pages within system
296 memory (see Documentation/mm/page_migration.rst) but the steps are split
301 The device driver has to pass a ``struct vm_area_struct`` to
302 migrate_vma_setup() so the mmap_read_lock() or mmap_write_lock() needs to
308 the pointer to migrate_vma_setup(). The ``args->flags`` field is used to
310 ``MIGRATE_VMA_SELECT_SYSTEM`` will only migrate system memory and
312 device private memory. If the latter flag is set, the ``args->pgmap_owner``
313 field is used to identify device private pages owned by the driver. This
314 avoids trying to migrate device private pages residing in other devices.
315 Currently only anonymous private VMA ranges can be migrated to or from
316 system memory and device private memory.
318 One of the first steps migrate_vma_setup() does is to invalidate other
321 walks to fill in the ``args->src`` array with PFNs to be migrated.
323 ``struct mmu_notifier_range`` with the ``event`` field set to
324 ``MMU_NOTIFY_MIGRATE`` and the ``owner`` field set to
325 the ``args->pgmap_owner`` field passed to migrate_vma_setup(). This
326 allows the device driver to skip the invalidation callback and only
331 entry results in a valid "zero" PFN stored in the ``args->src`` array.
332 This lets the driver allocate device private memory and clear it instead
333 of copying a page of zeros. Valid PTE entries to system memory or
335 from the LRU (if system memory since device private pages are not on
338 migrate_vma_setup() also clears the ``args->dst`` array.
340 3. The device driver allocates destination pages and copies source pages to
343 The driver checks each ``src`` entry to see if the ``MIGRATE_PFN_MIGRATE``
345 can also choose to skip migrating a page by not filling in the ``dst``
349 system memory page, locks the page with ``lock_page()``, and fills in the
355 invalidate device private MMU mappings and copy device private memory
356 to system memory or another device private page. The core Linux kernel
357 handles CPU page table invalidations so the device driver only has to
360 The driver can use ``migrate_pfn_to_page(src[i])`` to get the
361 ``struct page`` of the source and either copy the source page to the
362 destination or clear the destination device private memory if the pointer
363 is ``NULL`` meaning the source page was not populated in system memory.
377 information is now copied to destination ``struct page`` finalizing the
390 page's page table entry and releases the reference to the source and
397 Exclusive access memory
400 Some devices have features such as atomic PTE bits that can be used to implement
401 atomic access to system memory. To support atomic operations to a shared virtual
402 memory page such a device needs access to that page which is exclusive of any
404 can be used to make a memory range inaccessible from userspace.
407 entries. Any attempt to access the swap entry results in a fault which is
410 it will no longer have exclusive access to the page. Exclusive access is
411 guaranteed to last until the driver drops the page lock and page reference, at
414 Memory cgroup (memcg) and rss accounting
417 For now, device memory is accounted as any regular page in rss counters (either
419 file backed page, or shmem if device page is used for shared memory). This is a
420 deliberate choice to keep existing applications, that might start using device
421 memory without knowing about it, running unimpacted.
424 device memory and not a lot of regular system memory and thus not freeing much
425 system memory. We want to gather more real world experience on how applications
426 and system react under memory pressure in the presence of device memory before
427 deciding to account device memory differently.
430 Same decision was made for memory cgroup. Device memory pages are accounted
431 against same memory cgroup a regular page would be accounted to. This does
432 simplify migration to and from device memory. This also means that migration
433 back from device memory to regular memory cannot fail because it would
434 go above memory cgroup limit. We might revisit this choice later on once we
435 get more experience in how device memory is used and its impact on memory
439 Note that device memory can never be pinned by a device driver nor through GUP
440 and thus such memory is always free upon process exit. Or when last reference
441 is dropped in case of shared memory or file backed memory.