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5 The following is a summary of the SMBus protocol. It applies to
11 which is a subset from the I2C protocol. Fortunately, many devices use
14 If you write a driver for some I2C device, please try to use the SMBus
21 Below is a list of SMBus protocol operations, and the functions executing
23 don't match these function names. For some of the operations which pass a
25 a different protocol operation entirely.
27 Each transaction type corresponds to a functionality flag. Before calling a
28 transaction function, a device driver should always check (just once) for
43 A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
45 get a 10 bit I2C address.
46 Comm (8 bits) Command byte, a data byte which often selects a register on
48 Data (8 bits) A plain data byte. DataLow and DataHigh represent the low and
49 high byte of a 16 bit word.
50 Count (8 bits) A data byte containing the length of a block operation.
60 This sends a single bit to the device, at the place of the Rd/Wr bit::
62 S Addr Rd/Wr [A] P
72 This reads a single byte from a device, without specifying a device
74 others, it is a shorthand if you want to read the same register as in
77 S Addr Rd [A] [Data] NA P
87 This operation is the reverse of Receive Byte: it sends a single byte
88 to a device. See Receive Byte for more information.
92 S Addr Wr [A] Data [A] P
102 This reads a single byte from a device, from a designated register.
105 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P
115 This operation is very like Read Byte; again, data is read from a
116 device, from a designated register that is specified through the Comm
117 byte. But this time, the data is a complete word (16 bits)::
119 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
133 This writes a single byte to a device, to a designated register. The
139 S Addr Wr [A] Comm [A] Data [A] P
150 of data are written to a device, to the designated register that is
153 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
165 This command selects a device register (through the Comm byte), sends
168 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
169 Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
179 This command reads a block of up to 32 bytes from a device, from a
185 S Addr Wr [A] Comm [A]
186 Sr Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
197 a device, to a designated register that is specified through the
202 S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
213 This command selects a device register (through the Comm byte), sends
216 S Addr Wr [A] Comm [A] Count [A] Data [A] ...
217 Sr Addr Rd [A] [Count] A [Data] ... A P
225 This command is sent from a SMBus device acting as a master to the
226 SMBus host acting as a slave.
232 [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]
238 * I2C bus drivers trigger SMBus Host Notify by a call to
241 client->irq assigned to a Host Notify IRQ if no one else specified another.
251 PEC adds a CRC-8 error-checking byte to transfers using it, immediately
259 the specification. It is a higher-layer protocol which uses the
272 The SMBus alert protocol allows several SMBus slave devices to share a
288 and Write operations, except these do not have a Count byte. They are
293 but the SMBus layer places a limit of 32 bytes.
301 This command reads a block of bytes from a device, from a
304 S Addr Wr [A] Comm [A]
305 Sr Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
316 a device, to a designated register that is specified through the
322 S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P