Lines Matching full:sequencer

12 - A HW sequencer with RW DMA capability to system memory
18 Hardware sequencer within the THC is responsible for transferring (via DMA) data from touch devices
98                      |  |       HW Sequencer        |  |
118 HW Sequencer includes THC major logic, it gets instruction from MMIO registers to control
121 type. That means THC HW Sequencer understands HIDSPI/HIDI2C transfer protocol, and handle
196 packet reading, THC hardware sequencer will first read incoming input packet size, then compare
480 - THC Sequencer reads the input report header by transmitting read approval as a signal
482 - THC Sequencer executes a Input Report Body Read operation corresponding to the value
484 - THC DMA engine begins fetching data from the THC Sequencer and writes to host memory
486   THC Sequencer signals all data has been read or the THC DMA Read Engine reaches the
488 - The THC Sequencer checks for the “Last Fragment Flag” bit in the Input Report Header.
489   If it is clear, the THC Sequencer enters an idle state.
490 - If the “Last Fragment Flag” bit is enabled the THC Sequencer enters End-of-Frame Processing.
492 THC Sequencer End of Frame Processing:
540   THC Sequencer issues a READ request over the I2C bus. The HIDI2C device returns the
542 - THC Sequencer continues the Read operation as per the size of data indicated in the
544 - THC DMA engine begins fetching data from the THC Sequencer and writes to host memory
546   plus the remaining data to RxDMA buffer. This process continues until the THC Sequencer
549 - THC Sequencer enters End-of-Input Report Processing.
554 THC Sequencer End of Input Report Processing: