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1 .. SPDX-License-Identifier: GPL-2.0
4 Chrome OS ACPI Device
7 Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
8 The plug and play ID of a Chrome OS ACPI device is GGL0001 and the hardware ID is
11 .. flat-table:: Supported ACPI Objects
13    :header-rows: 1
15    * - Object
16      - Description
18    * - CHSW
19      - Chrome OS switch positions
21    * - HWID
22      - Chrome OS hardware ID
24    * - FWID
25      - Chrome OS firmware version
27    * - FRID
28      - Chrome OS read-only firmware version
30    * - BINF
31      - Chrome OS boot information
33    * - GPIO
34      - Chrome OS GPIO assignments
36    * - VBNV
37      - Chrome OS NVRAM locations
39    * - VDTA
40      - Chrome OS verified boot data
42    * - FMAP
43      - Chrome OS flashmap base address
45    * - MLST
46      - Chrome OS method list
48 CHSW (Chrome OS switch positions)
50 This control method returns the switch positions for Chrome OS specific hardware switches.
53 ----------
56 Result code:
57 ------------
60 .. flat-table::
63    * - 0x00000002
64      - Recovery button was pressed when x86 firmware booted.
66    * - 0x00000004
67      - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
70    * - 0x00000020
71      - Developer switch was enabled when x86 firmware booted.
73    * - 0x00000200
74      - Firmware write protection was disabled when x86 firmware booted. (required if
79 HWID (Chrome OS hardware ID)
84 ----------
87 Result code:
88 ------------
89 A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
94 FWID (Chrome OS firmware version)
100 ----------
103 Result code:
104 ------------
105 A null-terminated ASCII string containing the complete firmware version for the rewritable
108 FRID (Chrome OS read-only firmware version)
110 This control method returns the firmware version for the read-only portion of the main
114 ----------
117 Result code:
118 ------------
119 A null-terminated ASCII string containing the complete firmware version for the read-only
122 BINF (Chrome OS boot information)
127 ----------
130 Result code:
131 ------------
133 .. code-block::
143 .. flat-table::
145    :header-rows: 1
147    * - Field
148      - Format
149      - Description
151    * - Reserved1
152      - DWORD
153      - Set to 256 (0x100). This indicates this field is no longer used.
155    * - Reserved2
156      - DWORD
157      - Set to 256 (0x100). This indicates this field is no longer used.
159    * - Active EC firmware
160      - DWORD
161      - The EC firmware which was used during boot.
163        - 0 - Read-only (recovery) firmware
164        - 1 - Rewritable firmware.
166        Set to 0 if EC firmware is always read-only.
168    * - Active Main Firmware Type
169      - DWORD
170      - The main firmware type which was used during boot.
172        - 0 - Recovery
173        - 1 - Normal
174        - 2 - Developer
175        - 3 - netboot (factory installation only)
179    * - Reserved5
180      - DWORD
181      - Set to 256 (0x100). This indicates this field is no longer used.
183 GPIO (Chrome OS GPIO assignments)
185 This control method returns information about Chrome OS specific GPIO assignments for
186 Chrome OS hardware, so the kernel can directly control that hardware.
189 ----------
192 Result code:
193 ------------
194 .. code-block::
201                         Controller Offset  //DWORD
209                         Controller Offset  //DWORD
214 Where ASCIIZ means a null-terminated ASCII string.
216 .. flat-table::
218    :header-rows: 1
220    * - Field
221      - Format
222      - Description
224    * - Signal Type
225      - DWORD
226      - Type of GPIO signal
228        - 0x00000001 - Recovery button
229        - 0x00000002 - Developer mode switch
230        - 0x00000003 - Firmware write protection switch
231        - 0x00000100 - Debug header GPIO 0
232        - ...
233        - 0x000001FF - Debug header GPIO 255
237    * - Attributes
238      - DWORD
239      - Signal attributes as bitfields:
241        - 0x00000001 - Signal is active-high (for button, a GPIO value
246    * - Controller Offset
247      - DWORD
248      - GPIO number on the specified controller.
250    * - Controller Name
251      - ASCIIZ
252      - Name of the controller for the GPIO.
254        "NM10" - Intel NM10 chip
256 VBNV (Chrome OS NVRAM locations)
262 ----------
265 Result code:
266 ------------
267 .. code-block::
270                 NV Storage Block Offset  //DWORD
274 .. flat-table::
276    :header-rows: 1
278    * - Field
279      - Format
280      - Description
282    * - NV Storage Block Offset
283      - DWORD
284      - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
285        the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
288    * - NV Storage Block Size
289      - DWORD
290      - Size in bytes of the verified boot non-volatile storage block.
292 FMAP (Chrome OS flashmap address)
298 ----------
301 NoneResult code:
302 ----------------
306 VDTA (Chrome OS verified boot data)
312 ----------
315 Result code:
316 ------------
321 This control method returns the SHA-1 or SHA-256 hash that is read out of the Management
322 Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that
327 ----------
330 Result code:
331 ------------
334 MLST (Chrome OS method list)
336 This control method returns a list of the other control methods supported by the Chrome OS
340 ----------
343 Result code:
344 ------------
345 A package containing a list of null-terminated ASCII strings, one for each control method
346 supported by the Chrome OS hardware device, not including the MLST method itself.
349 .. code-block::