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2 Xillybus driver for generic FPGA interface
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
22 -- Host never reads from the FPGA
23 -- Channels, pipes, and the message channel
24 -- Data streaming
25 -- Data granularity
26 -- Probing
27 -- Buffer allocation
28 -- The "nonempty" message (supporting poll)
35 ----------
37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which
48 level, even lower than assembly language. In order to allow FPGA designers to
50 again, pre-designed building blocks, IP cores, are often used. These are the
51 FPGA parallels of library functions. IP cores may implement certain
57 One of the daunting tasks in FPGA design is communicating with a fullblown
59 low-level bus protocol and the somewhat higher-level interface with the host
60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
61 function is a well-known one (e.g. a video adapter card, or a NIC), it can
62 make sense to design the FPGA's interface logic specifically for the project.
63 A special driver is then written to present the FPGA as a well-known interface
65 FPGA differently than any device on the bus.
67 It's however common that the desired data communication doesn't fit any well-
73 interface logic for the FPGA, and write a simple ad-hoc driver for the kernel.
76 -----------------
79 elementary data transport between an FPGA and the host, providing pipe-like
80 data streams with a straightforward user interface. It's intended as a low-
81 effort solution for mixed FPGA-host projects, for which it makes sense to
82 have the project-specific part of the driver running in a user-space program.
84 Since the communication requirements may vary significantly from one FPGA
92 just like any pipe file. On the FPGA side, hardware FIFOs are used to stream
93 the data. This is contrary to a common method of communicating through fixed-
111 --------------
115 names of these files depend on the IP core that is loaded in the FPGA (see
116 Probing below). To communicate with the FPGA, open the device file that
125 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
130 * Supporting non-blocking I/O (by setting O_NONBLOCK on open() ).
142 ---------------
146 some data has been submitted and acknowledged by the FPGA. This slows down
148 require data at a constant rate: There is no data transmitted to the FPGA
154 For FPGA to host pipes, asynchronous pipes allow data transfer from the FPGA
159 In summary, for synchronous pipes, data between the host and FPGA is
170 --------------
173 to the user logic at the FPGA. Such a pipe is also seekable on the host API.
175 FPGA side to the seekable stream. Reading or writing to a certain address in
184 ------------------------
194 which execute the DMA-related operations on the bus.
197 ---------------
199 Each pipe has a number of attributes which are set when the FPGA component
204 * is_writebuf: The pipe's direction. A non-zero value means it's an FPGA to
205 host pipe (the FPGA "writes").
208 host and FPGA.
212 * allowpartial: A non-zero value means that a read() or write() (whichever
214 choice is a non-zero value, to match standard UNIX behavior.
216 * synchronous: A non-zero value means that the pipe is synchronous. See
223 * exclusive_open: A non-zero value forces exclusive opening of the associated
227 * seekable: A non-zero value indicates that the pipe is seekable. See
230 * supports_nonempty: A non-zero value (which is typical) indicates that the
234 Host never reads from the FPGA
235 ------------------------------
240 quite likely as a result of an accidental reprogramming of the FPGA while the
247 reading from the device's register space. All communication from the FPGA to
250 invoked. Rather, the FPGA prepares a small buffer which contains short
253 This mechanism is used on non-PCIe buses as well for the sake of uniformity.
257 ----------------------------------------
260 a data channel between the FPGA and the host. The distinction between channels
261 and pipes is necessary only because of channel 0, which is used for interrupt-
262 related messages from the FPGA, and has no pipe attached to it.
265 --------------
267 Even though a non-segmented data stream is presented to the user at both
269 for each channel. For the sake of illustration, let's take the FPGA to host
271 FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the
272 buffer is full, the FPGA informs the host about that (appending a
276 FPGA's buffer control register, allowing the buffer's overwriting. Flow
279 This is not good enough for creating a TCP/IP-like stream: If the data flow
283 XILLYMSG_OPCODE_RELEASEBUF message, through which the FPGA informs not just
286 But the FPGA will submit a partially filled buffer only if directed to do so
289 the FPGA to submit a DMA buffer as soon as it can. This timeout mechanism
293 A similar setting is used in the host to FPGA direction. The handling of
295 driver to submit all data it has in the buffers to the FPGA, by issuing a
300 and yet enjoy a stream-like interface.
307 ----------------
309 The data arrives or is sent at the FPGA as 8, 16 or 32 bit wide words, as
315 FPGA, so the transmission of up to one word may be held until it's fully
318 This somewhat complicates the handling of host to FPGA streams, because
320 the FPGA, and hence can't be sent. To prevent loss of data, these leftover
325 -------
328 loads and their attributes depend on the Xillybus IP core in the FPGA. During
330 Interface Description Table (IDT), is sent from the FPGA to the host. The
333 1. Acquire the length of the IDT, so a buffer can be allocated for it. This
342 -----------------
367 ----------------------------------------
370 catch regarding the FPGA to host direction: The FPGA may have filled a DMA
372 the buffer's submission by the FPGA, there would be a possibility that the
373 FPGA side has sent data, but a select() call would still block, because the
375 XILLYMSG_OPCODE_NONEMPTY messages sent by the FPGA when a channel goes from