Lines Matching full:hardware

35 hardware level. A couple of wiki pages by Texas Instruments and Analog
43 hardware sits at the lowest. The MUSB controller driver abstract the
44 MUSB controller hardware to the Linux USB stack::
65       |   MUSB Controller Hardware    |
69 sitting in between the controller driver and the controller hardware.
97 goes through a few steps, basically allocating the controller hardware
256 	 * Set dyn_fifo to avoid reading EP config from hardware.
266 driver data of the MUSB controller hardware and pass it on to the MUSB
268 controller hardware responsible for sending/receiving the USB data.
287 PHY driver when the controller hardware itself is about to be released.
290 basic set of features of the JZ4740 controller hardware. When writing an
291 musb glue layer for a more complex controller hardware, you might need
315 layer adds the controller hardware device to Linux kernel device
333 MUSB controller hardware (line 5) and disable the clock (line 6),
341 Additionally to the MUSB controller hardware basic setup and
375 Here the glue layer mostly has to read the relevant hardware registers
413 in order for the controller hardware to call the handler back when an
414 IRQ comes from the controller hardware. The interrupt handler is now
423 describing the hardware capabilities of your controller hardware, which
426 Platform data is specific to your hardware, though it may cover a broad
541 operation related to the controller hardware specifics. This is done
544 Defining the OTG capability of the controller hardware, the multipoint
547 endpoints of the controller hardware, including endpoint 0: here we have
549 of the RAM address bus for the MUSB controller hardware. This
551 configure endpoints by reading the relevant controller hardware
562 if the controller hardware may be used as ``MUSB_HOST`` only,
576 limitations. These quirks may be due to some hardware bugs, or simply be
582 controller hardware you are working on.
598 	 * Set dyn_fifo to avoid reading EP config from hardware.
608 the fact that the controller hardware is missing registers that are used
612 endpoints configuration from the hardware, so we use line 12 instruction
625 in the controller hardware, or ``FIFO_RX`` to receive packets from
626 hardware), and maxpacket defines the maximum size of each data packet
674 undefined hardware state, since this MUSB controller hardware is used in
683 for others controller hardware eventually.
704 I would also like to thank the Qi-Hardware community at large for its