Lines Matching +full:wait +full:- +full:on +full:- +full:write
6 -----------
12 ------------
14 The SoundWire 1.x specification provides a mechanism to speed-up
17 solution based on the Bulk Payload Transport (BPT) definitions.
20 one byte per frame with write/read commands. With a typical 48kHz
27 (1) Each frame can only support a read or a write transfer, with a
28 10-byte overhead per frame (header and footer response).
36 Port 0, and likewise the Manager SHALL expose audio-like Ports
40 (4) The BRA transport efficiency depends on the available
41 bandwidth. If there are no on-going audio transfers, the entire
44 BTP/BRA, the frame should rely on a large number of columns and
52 (6) The regular read/write commands can be issued in parallel with
61 need to be spaced in time or flow-controlled.
68 transfer can be started early on without data being ready.
72 (10) The address is represented with 32 bits and does not rely on
78 --------------
84 (1) A CRC on the 7-byte header. This CRC helps the Peripheral Device
88 (2) A CRC on the data block (header excluded). This CRC is
89 transmitted as the last-but-one byte in the packet, prior to the
104 -------------
108 to start on a new SoundWire Row, and the scale of data may vary.
112 +---+--------------------------------------------+
116 + +--------------------------------------------+
118 + O +--------------------------------------------+
120 + M +--------------------------------------------+
127 + +--------------------------------------------+
129 + +--------------------------------------------+
131 +---+--------------------------------------------+
137 - HSTART = 1
138 - HSTOP = N - 1
139 - Sampling Interval = N
140 - WordLength = N - 1
143 -----------------------
150 this would only be beneficial for single-link solutions.
155 streams, possibly in parallel - the links are really independent.
158 --------------------
166 (2) Flow-control capabilities and retransmission based on the
170 Bi-directional handling
171 -----------------------
175 Target device. On the Peripheral device, the BRA protocol is handled
176 by a single DP0 data port, and at the low-level the bus ownership can
180 On the host side, most implementations rely on a Port-like concept,
182 (Host->Peripheral and Peripheral->Host). The amount of data
197 retry a transfer in case of errors. However, as for the flow-control
206 Manager level, so the low-level BPT/BRA details must be hidden in
207 Manager-specific code. For example the Cadence IP format above is not
212 Manager-specific code.
214 The host BRA driver may also have restrictions on pages allocated for
215 DMA, or other host-DSP communication protocols. The codec driver
219 Concurrency between BRA and regular read/write
222 The existing 'nread/nwrite' API already relies on a notion of start
227 mutex for regular read/write and BRA is a show-stopper. Independent
234 In addition, the 'sdw_msg' structure hard-codes support for 16-bit
236 support based on native 32-bit addresses. A separate API with
239 One possible strategy to speed-up all initialization tasks would be to
242 to wait for the BRA transfers to complete. This would allow for a
244 the BRA API must support async transfers and expose a separate wait
249 ------------------------
253 - sdw_bpt_send_async(bpt_message)
256 implementation-defined capabilities (typically DMA or IPC
260 needs to wait for completion of the requested transfer.
262 - sdw_bpt_wait()
272 Existing codec drivers rely on regmap to download firmware to
274 send/wait API suggested above, so at a high-level it would seem
276 is available or not, and use a regular read-write command channel in
282 ----------------
295 Peripherals on a link and some of them do not support DP0, the
296 write commands to program DP0 registers will generate harmless
297 COMMAND_IGNORED responses that will be wired-ORed with
300 the information on the Target device can be added only in the
304 machine driver will not create a dailink relying on DP0. The
307 (3) The stream concept relies on a set of master_rt and slave_rt
315 Manager/Link, so the BRA stream handling does not rely on the
316 concept of multi-link aggregation allowed by regular DAI links.
319 -----------------
324 format and bandwidth may vary between read and write commands.
326 In addition, on Intel HDaudio Intel platforms the DMAs need to be
328 transfer. The format is based on 192kHz 32-bit samples, and the number
335 but at the platform-level, e.g. for Intel the data sizes must be