Lines Matching +full:inter +full:- +full:processor
1 .. SPDX-License-Identifier: GPL-2.0
34 ------------------------
51 ---------
61 -------------------------------------
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
89 The IPU6 has its own scalar processor where the firmware run at and an internal
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
101 .. code-block:: none
113 generic PCI DMA ops to ask IOMMU to do the additional mapping if VT-d
121 component includes 3 entries - manifest, metadata and module data. Manifest and
124 directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates
135 inter-processor communication mechanism between the IPU scalar processors and
150 setting the scalar processor control status register.
155 IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers. It can
156 capture image pixel data from camera sensors or other MIPI CSI-2 output devices.
158 D-PHYs and CSI-2 ports lane mapping
159 -----------------------------------
161 The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and
162 Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL
163 D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an
164 adaptional layer between D-PHY and CSI-2 receiver controller which includes port
165 configuration, PHY wrapper or private test interfaces for D-PHY. There are 3
166 D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and
167 ``ipu6-isys-dwc-phy.c`` program the above 3 D-PHYs in IPU6.
169 Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake,
170 there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
171 see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper
172 Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
173 maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
174 lanes so IPU6 support maximum 6 CSI-2 ports.
176 .. Note:: Each pair of CSI-2 two ports is a single unit that can share the data
177 lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
178 maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
179 port 0 with 2 data lanes can work together with CSI-2 port 1 with 2
180 data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1
181 will not be available as the 4 data lanes are shared by CSI-2 port 0
185 ------------------