Lines Matching refs:UMC
199 and each GPU data fabric contains four Unified Memory Controllers (UMC).
200 Each UMC contains eight channels. Each UMC channel controls one 128-bit
204 While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC
210 GPU UMC -> EDAC CSROW
211 GPU UMC channel -> EDAC CHANNEL
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
221 - CPU UMCs use 1 channel, In this case UMC = EDAC channel. This follows the
223 - CPU UMCs use up to 4 chip selects, So UMC chip select = EDAC CSROW.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
257 │ ├── csrow 0 # UMC 0
258 │ │ ├── channel 0 # Each UMC has 8 channels
259 │ │ ├── channel 1 # size of each channel is 2 GB, so each UMC has 16 GB
266 │ ├── csrow 1 # UMC 1
271 │ ├── csrow 3 # UMC 3