Lines Matching +full:reference +full:- +full:sync
1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
81 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is selected to drive dpll
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not selected to drive
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
97 for automatic-only DPLL devices where mode cannot be switched to manual.
105 - ``DPLL_PIN_OPERSTATE_ACTIVE`` - pin is qualified and actively used
107 - ``DPLL_PIN_OPERSTATE_STANDBY`` - pin is qualified but not actively
109 - ``DPLL_PIN_OPERSTATE_NO_SIGNAL`` - pin does not have a valid signal
110 - ``DPLL_PIN_OPERSTATE_QUAL_FAILED`` - pin signal failed qualification
119 1) Set on a pin - the configuration is a property of the pin itself and
122 2) Set on a pin-dpll tuple - the configuration affects only selected
126 MUX-type pins
129 A pin can be MUX-type, it aggregates child pins and serves as a pin
130 multiplexer. One or more pins are registered with MUX-type instead of
132 Pins registered with a MUX-type pin provide user with additional nested
137 ``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested
141 'clock-id': 282574471561216,
142 'module-name': 'ice',
145 'parent-pin': [
146 {'parent-id': 2, 'state': 'connected'},
147 {'parent-id': 3, 'state': 'disconnected'}
149 'type': 'synce-eth-port'
152 Only one child pin can provide its signal to the parent MUX-type pin at
187 Child pin of MUX-type pin is not capable of automatic input pin selection,
188 in order to configure active input of a MUX-type pin, the user needs to
190 as described in the ``MUX-type pins`` chapter.
196 on a pin and its parent dpll device. If pin-dpll phase offset measurement
203 curr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N}
247 offset values are fractional with 3-digit decimal places and shell be
255 source. However, some DPLL (Digital Phase-Locked Loop) devices may offer
275 - ``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET`` in PPM (parts per million)
276 - ``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT`` in PPT (parts per trillion)
279 ``pin-parent-device`` nest. Two FFO types are defined:
281 - ``DPLL_FFO_PORT_RXTX_RATE`` - RX vs TX symbol rate offset (top-level)
282 - ``DPLL_FFO_PIN_DEVICE`` - pin vs parent DPLL offset (per-parent)
307 Embedded SYNC
310 Device may provide ability to use Embedded SYNC feature. It allows
311 to embed additional SYNC signal into the base frequency of a pin - a one
312 special pulse of base frequency signal every time SYNC signal pulse
313 happens. The user can configure the frequency of Embedded SYNC.
314 The Embedded SYNC capability is always related to a given base frequency
315 and HW capabilities. The user is provided a range of Embedded SYNC
320 ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency
321 ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC
325 ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC
328 Reference SYNC
331 The device may support the Reference SYNC feature, which allows the combination
336 enables the provision of a high-quality loop bandwidth signal from an external
340 Reference SYNC. To control this feature, the user must request a desired
347 requesting configuration of the Reference
348 SYNC feature
349 ``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature
350 ``DPLL_A_PIN_STATE`` state of Reference SYNC connection
377 (EUI-64), as defined by the
388 (EUI-64), as defined by the
412 (EUI-64), as defined by the
429 (EUI-64), as defined by the
504 ``DPLL_CMD_DEVICE_SET`` - to target a dpll device, the user provides
508 ``DPLL_CMD_PIN_SET`` - to target a pin user must provide a
519 For MUX-type pins the ``DPLL_A_PIN_STATE`` attribute is configured in
527 Configuration pre-defined enums
530 .. kernel-doc:: include/uapi/linux/dpll.h
537 There is one multicast group that is used to notify user-space apps via
570 users. Multiple driver instances can obtain reference to it with
583 - dpll_pin_register() - register pin with a dpll device,
584 - dpll_pin_on_pin_register() - register pin with another MUX type pin.
593 - after successful change was requested on dpll subsystem, the subsystem
595 - requested by device driver with dpll_device_change_ntf() or
603 - ``.mode_get``,
604 - ``.lock_status_get``.
608 - ``.state_on_dpll_get`` (pins registered with dpll device),
609 - ``.state_on_pin_get`` (pins registered with parent pin),
610 - ``.direction_get``.
613 ``-EOPNOTSUPP`` is returned in case of absence of specific handler.
618 .. code-block:: c
636 .. code-block:: c
639 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
640 if (IS_ERR(bp->dpll)) {
641 err = PTR_ERR(bp->dpll);
642 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
646 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
651 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
652 if (IS_ERR(bp->sma[i].dpll_pin)) {
653 err = PTR_ERR(bp->dpll);
657 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
658 &bp->sma[i]);
660 dpll_pin_put(bp->sma[i].dpll_pin);
667 .. code-block:: c
670 --i;
671 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
672 dpll_pin_put(bp->sma[i].dpll_pin);
674 dpll_device_put(bp->dpll);
686 This is done by exposing a pin to the netdevice - attaching pin to the