Lines Matching +full:pcie +full:- +full:host +full:- +full:1
1 .. SPDX-License-Identifier: GPL-2.0
12 Address space is handled via HDM (Host Managed Device Memory) decoders
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
25 multiple Host Bridges and endpoints while another may opt for fault tolerance
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
30 dictates which endpoints can participate in which Host Bridge decode regimes.
31 Each PCIe Switch in the path between the root and an endpoint introduces a point
33 given range only decodes to one Host Bridge, but that Host Bridge may in turn
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
40 Ports. Each of those Root Ports are connected to 2-way switches with endpoints
43 # cxl list -BEMPu -b cxl_test
50 "host":"cxl_host_bridge.1",
54 "host":"cxl_switch_uport.1",
58 "host":"mem2",
64 "numa_node":1,
65 "host":"cxl_mem.1"
70 "host":"mem6",
76 "numa_node":1,
77 "host":"cxl_mem.5"
84 "host":"cxl_switch_uport.3",
88 "host":"mem8",
94 "numa_node":1,
95 "host":"cxl_mem.7"
100 "host":"mem4",
106 "numa_node":1,
107 "host":"cxl_mem.3"
116 "host":"cxl_host_bridge.0",
120 "host":"cxl_switch_uport.0",
124 "host":"mem1",
131 "host":"cxl_mem.0"
136 "host":"mem5",
143 "host":"cxl_mem.4"
150 "host":"cxl_switch_uport.2",
154 "host":"mem7",
161 "host":"cxl_mem.6"
166 "host":"mem3",
173 "host":"cxl_mem.2"
185 its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
190 Continuing the RAID analogy, disks have both topology metadata and on-device
193 by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches
195 objects. Conversely for hot-unplug / removal scenarios, there is no need for
196 the Linux PCI core to tear down switch-level CXL resources because the endpoint
197 ->remove() event cleans up the port data that was established to support that
203 # cxl list -BDMu -d root -m mem3
209 "decoder":"decoder3.1",
227 "nr_targets":1
234 "nr_targets":1
244 "host":"cxl_mem.2"
254 Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
255 memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
256 that only targets a single Host Bridge.
261 # cxl list -MDu -d 3.2
271 "host":"cxl_mem.0"
279 "host":"cxl_mem.4"
287 "host":"cxl_mem.6"
295 "host":"cxl_mem.2"
306 "nr_targets":1
320 -----------------
322 .. kernel-doc:: drivers/cxl/pci.c
325 .. kernel-doc:: drivers/cxl/pci.c
328 .. kernel-doc:: drivers/cxl/mem.c
331 .. kernel-doc:: drivers/cxl/cxlmem.h
334 .. kernel-doc:: drivers/cxl/core/memdev.c
338 --------
339 .. kernel-doc:: drivers/cxl/port.c
343 --------
344 .. kernel-doc:: drivers/cxl/cxl.h
347 .. kernel-doc:: drivers/cxl/cxl.h
350 .. kernel-doc:: drivers/cxl/acpi.c
353 .. kernel-doc:: drivers/cxl/core/hdm.c
356 .. kernel-doc:: drivers/cxl/core/hdm.c
359 .. kernel-doc:: drivers/cxl/core/cdat.c
362 .. kernel-doc:: drivers/cxl/core/port.c
365 .. kernel-doc:: drivers/cxl/core/port.c
368 .. kernel-doc:: drivers/cxl/core/pci.c
371 .. kernel-doc:: drivers/cxl/core/pci.c
374 .. kernel-doc:: drivers/cxl/core/pmem.c
377 .. kernel-doc:: drivers/cxl/core/pmem.c
380 .. kernel-doc:: drivers/cxl/core/regs.c
383 .. kernel-doc:: drivers/cxl/core/regs.c
386 .. kernel-doc:: drivers/cxl/core/mbox.c
389 .. kernel-doc:: drivers/cxl/core/mbox.c
392 .. kernel-doc:: drivers/cxl/core/features.c
398 -----------
399 .. kernel-doc:: drivers/cxl/core/region.c
402 .. kernel-doc:: drivers/cxl/core/region.c
409 -------------------
411 .. kernel-doc:: include/uapi/linux/cxl_mem.h
414 .. kernel-doc:: include/uapi/linux/cxl_mem.h