Lines Matching +full:device +full:- +full:id +full:- +full:base
1 .. SPDX-License-Identifier: GPL-2.0
4 Coherent Device Attribute Table (CDAT)
10 be enumerated at runtime (after device hotplug, for example).
13 DPA - Device Physical Address, used by the CXL device to denote the address
14 it supports for that device.
16 DSMADHandle - A device unique handle that is associated with a DPA range
21 Device Scoped Memory Affinity Structure (DSMAS)
24 The DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
27 This table is used by Linux in conjunction with the Device Scoped Latency and
29 attributes of the CXL device itself.
35 Length : 0018 <- 24d, size of structure
39 DPA Base : 0000000040000000 <- 1GiB base
40 DPA Length : 0000000080000000 <- 2GiB size
44 Device Scoped Latency and Bandwidth Information Structure (DSLBIS)
48 performance attributes of a CXL device. The DSLBIS contains latency
55 Length : 18 <- 24d, size of structure
56 Handle : 0001 <- DSMAS handle
57 Flags : 00 <- Matches flag field for HMAT SLLBIS
58 Data Type : 00 <- Latency
59 Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
60 Entry : 010000000000 <- First byte used here, CXL LTC
65 Length : 18 <- 24d, size of structure
66 Handle : 0001 <- DSMAS handle
67 Flags : 00 <- Matches flag field for HMAT SLLBIS
68 Data Type : 03 <- Bandwidth
69 Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
70 Entry : 020000000000 <- First byte used here, CXL BW
81 from the device to the root port where a switch is part of the path.
87 Length : 20 <- 32d, length of record, including SSLB entries
88 Data Type : 00 <- Latency
90 Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
92 <- SSLB Entry 0
93 Port X ID : 0100 <- First port, 0100h represents an upstream port
94 Port Y ID : 0000 <- Second port, downstream port 0
95 Latency : 0100 <- Port latency
97 <- SSLB Entry 1
98 Port X ID : 0100
99 Port Y ID : 0001
106 Length : 18 <- 24d, length of record, including SSLB entry
107 Data Type : 03 <- Bandwidth
109 Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
111 <- SSLB Entry 0
112 Port X ID : 0100 <- First port, 0100h represents an upstream port
113 Port Y ID : FFFF <- Second port, FFFFh indicates any port
114 Bandwidth : 1200 <- Port bandwidth
118 generate "whole path performance" data for a CXL device.