Lines Matching +full:sa8775p +full:- +full:dp
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
12 # Use the combined qcom,snps-dwc3 instead
21 - compatible
26 - enum:
27 - qcom,ipq4019-dwc3
28 - qcom,ipq5018-dwc3
29 - qcom,ipq5332-dwc3
30 - qcom,ipq5424-dwc3
31 - qcom,ipq6018-dwc3
32 - qcom,ipq8064-dwc3
33 - qcom,ipq8074-dwc3
34 - qcom,ipq9574-dwc3
35 - qcom,msm8953-dwc3
36 - qcom,msm8994-dwc3
37 - qcom,msm8996-dwc3
38 - qcom,msm8998-dwc3
39 - qcom,qcm2290-dwc3
40 - qcom,qcs404-dwc3
41 - qcom,qcs615-dwc3
42 - qcom,qcs8300-dwc3
43 - qcom,qdu1000-dwc3
44 - qcom,sa8775p-dwc3
45 - qcom,sar2130p-dwc3
46 - qcom,sc7180-dwc3
47 - qcom,sc7280-dwc3
48 - qcom,sc8180x-dwc3
49 - qcom,sc8180x-dwc3-mp
50 - qcom,sc8280xp-dwc3
51 - qcom,sc8280xp-dwc3-mp
52 - qcom,sdm660-dwc3
53 - qcom,sdm670-dwc3
54 - qcom,sdm845-dwc3
55 - qcom,sdx55-dwc3
56 - qcom,sdx65-dwc3
57 - qcom,sdx75-dwc3
58 - qcom,sm4250-dwc3
59 - qcom,sm6115-dwc3
60 - qcom,sm6125-dwc3
61 - qcom,sm6350-dwc3
62 - qcom,sm6375-dwc3
63 - qcom,sm8150-dwc3
64 - qcom,sm8250-dwc3
65 - qcom,sm8350-dwc3
66 - qcom,sm8450-dwc3
67 - qcom,sm8550-dwc3
68 - qcom,sm8650-dwc3
69 - qcom,sm8750-dwc3
70 - qcom,x1e80100-dwc3
71 - qcom,x1e80100-dwc3-mp
72 - const: qcom,dwc3
78 "#address-cells":
81 "#size-cells":
86 power-domains:
90 required-opps:
96 - cfg_noc:: System Config NOC clock.
97 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
99 - iface:: System bus AXI clock.
100 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
102 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
107 clock-names:
117 interconnect-names:
119 - const: usb-ddr
120 - const: apps-usb
125 - pwr_event: Used for wakeup based on other power events.
126 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
129 {dp/dm}_hs_phy_irq and qusb2_phy_irq.
130 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
135 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
137 only on SoCs with non-QUSB2 targets with
139 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
143 interrupt-names:
147 qcom,select-utmi-as-pipe-clk:
154 wakeup-source: true
159 "^usb@[0-9a-f]+$":
164 wakeup-source: false
167 - compatible
168 - reg
169 - "#address-cells"
170 - "#size-cells"
171 - ranges
172 - clocks
173 - clock-names
174 - interrupts
175 - interrupt-names
178 - if:
183 - qcom,ipq4019-dwc3
184 - qcom,ipq5332-dwc3
189 clock-names:
191 - const: core
192 - const: sleep
193 - const: mock_utmi
195 - if:
200 - qcom,ipq8064-dwc3
205 - description: Master/Core clock, has to be >= 125 MHz
207 clock-names:
209 - const: core
211 - if:
216 - qcom,ipq9574-dwc3
217 - qcom,msm8953-dwc3
218 - qcom,msm8996-dwc3
219 - qcom,msm8998-dwc3
220 - qcom,qcs8300-dwc3
221 - qcom,sa8775p-dwc3
222 - qcom,sc7180-dwc3
223 - qcom,sc7280-dwc3
224 - qcom,sdm670-dwc3
225 - qcom,sdm845-dwc3
226 - qcom,sdx55-dwc3
227 - qcom,sdx65-dwc3
228 - qcom,sdx75-dwc3
229 - qcom,sm6350-dwc3
234 clock-names:
236 - const: cfg_noc
237 - const: core
238 - const: iface
239 - const: sleep
240 - const: mock_utmi
242 - if:
247 - qcom,ipq6018-dwc3
253 clock-names:
255 - items:
256 - const: core
257 - const: sleep
258 - const: mock_utmi
259 - items:
260 - const: cfg_noc
261 - const: core
262 - const: sleep
263 - const: mock_utmi
265 - if:
270 - qcom,ipq8074-dwc3
271 - qcom,qdu1000-dwc3
276 clock-names:
278 - const: cfg_noc
279 - const: core
280 - const: sleep
281 - const: mock_utmi
283 - if:
288 - qcom,ipq5018-dwc3
289 - qcom,msm8994-dwc3
290 - qcom,qcs404-dwc3
295 clock-names:
297 - const: core
298 - const: iface
299 - const: sleep
300 - const: mock_utmi
302 - if:
307 - qcom,sc8280xp-dwc3
308 - qcom,sc8280xp-dwc3-mp
309 - qcom,x1e80100-dwc3
310 - qcom,x1e80100-dwc3-mp
315 clock-names:
317 - const: cfg_noc
318 - const: core
319 - const: iface
320 - const: sleep
321 - const: mock_utmi
322 - const: noc_aggr
323 - const: noc_aggr_north
324 - const: noc_aggr_south
325 - const: noc_sys
327 - if:
332 - qcom,sdm660-dwc3
338 clock-names:
340 - items:
341 - const: cfg_noc
342 - const: core
343 - const: iface
344 - const: sleep
345 - const: mock_utmi
346 - items:
347 - const: cfg_noc
348 - const: core
349 - const: sleep
350 - const: mock_utmi
352 - if:
357 - qcom,qcm2290-dwc3
358 - qcom,qcs615-dwc3
359 - qcom,sar2130p-dwc3
360 - qcom,sc8180x-dwc3
361 - qcom,sc8180x-dwc3-mp
362 - qcom,sm6115-dwc3
363 - qcom,sm6125-dwc3
364 - qcom,sm8150-dwc3
365 - qcom,sm8250-dwc3
366 - qcom,sm8450-dwc3
367 - qcom,sm8550-dwc3
368 - qcom,sm8650-dwc3
369 - qcom,sm8750-dwc3
374 clock-names:
376 - const: cfg_noc
377 - const: core
378 - const: iface
379 - const: sleep
380 - const: mock_utmi
381 - const: xo
383 - if:
388 - qcom,sm8350-dwc3
394 clock-names:
397 - const: cfg_noc
398 - const: core
399 - const: iface
400 - const: sleep
401 - const: mock_utmi
402 - const: xo
404 - if:
409 - qcom,ipq5018-dwc3
410 - qcom,ipq6018-dwc3
411 - qcom,ipq8074-dwc3
412 - qcom,msm8953-dwc3
413 - qcom,msm8998-dwc3
419 interrupt-names:
422 - const: pwr_event
423 - const: qusb2_phy
424 - const: ss_phy_irq
426 - if:
431 - qcom,msm8996-dwc3
432 - qcom,qcs404-dwc3
433 - qcom,sdm660-dwc3
434 - qcom,sm6115-dwc3
435 - qcom,sm6125-dwc3
441 interrupt-names:
444 - const: pwr_event
445 - const: qusb2_phy
446 - const: hs_phy_irq
447 - const: ss_phy_irq
449 - if:
454 - qcom,ipq5332-dwc3
459 interrupt-names:
461 - const: pwr_event
462 - const: dp_hs_phy_irq
463 - const: dm_hs_phy_irq
465 - if:
470 - qcom,x1e80100-dwc3
476 interrupt-names:
479 - const: pwr_event
480 - const: dp_hs_phy_irq
481 - const: dm_hs_phy_irq
482 - const: ss_phy_irq
484 - if:
489 - qcom,ipq4019-dwc3
490 - qcom,ipq8064-dwc3
491 - qcom,msm8994-dwc3
492 - qcom,qcs615-dwc3
493 - qcom,qcs8300-dwc3
494 - qcom,qdu1000-dwc3
495 - qcom,sa8775p-dwc3
496 - qcom,sc7180-dwc3
497 - qcom,sc7280-dwc3
498 - qcom,sc8180x-dwc3
499 - qcom,sc8280xp-dwc3
500 - qcom,sdm670-dwc3
501 - qcom,sdm845-dwc3
502 - qcom,sdx55-dwc3
503 - qcom,sdx65-dwc3
504 - qcom,sdx75-dwc3
505 - qcom,sm4250-dwc3
506 - qcom,sm6350-dwc3
507 - qcom,sm8150-dwc3
508 - qcom,sm8250-dwc3
509 - qcom,sm8350-dwc3
510 - qcom,sm8450-dwc3
511 - qcom,sm8550-dwc3
512 - qcom,sm8650-dwc3
513 - qcom,sm8750-dwc3
519 interrupt-names:
522 - const: pwr_event
523 - const: hs_phy_irq
524 - const: dp_hs_phy_irq
525 - const: dm_hs_phy_irq
526 - const: ss_phy_irq
528 - if:
533 - qcom,sc8180x-dwc3-mp
534 - qcom,x1e80100-dwc3-mp
540 interrupt-names:
542 - const: pwr_event_1
543 - const: pwr_event_2
544 - const: hs_phy_1
545 - const: hs_phy_2
546 - const: dp_hs_phy_1
547 - const: dm_hs_phy_1
548 - const: dp_hs_phy_2
549 - const: dm_hs_phy_2
550 - const: ss_phy_1
551 - const: ss_phy_2
553 - if:
558 - qcom,sc8280xp-dwc3-mp
564 interrupt-names:
566 - const: pwr_event_1
567 - const: pwr_event_2
568 - const: pwr_event_3
569 - const: pwr_event_4
570 - const: hs_phy_1
571 - const: hs_phy_2
572 - const: hs_phy_3
573 - const: hs_phy_4
574 - const: dp_hs_phy_1
575 - const: dm_hs_phy_1
576 - const: dp_hs_phy_2
577 - const: dm_hs_phy_2
578 - const: dp_hs_phy_3
579 - const: dm_hs_phy_3
580 - const: dp_hs_phy_4
581 - const: dm_hs_phy_4
582 - const: ss_phy_1
583 - const: ss_phy_2
588 - |
589 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
590 #include <dt-bindings/interrupt-controller/arm-gic.h>
591 #include <dt-bindings/interrupt-controller/irq.h>
593 #address-cells = <2>;
594 #size-cells = <2>;
597 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
600 #address-cells = <2>;
601 #size-cells = <2>;
608 clock-names = "cfg_noc",
614 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
616 assigned-clock-rates = <19200000>, <150000000>;
623 interrupt-names = "pwr_event", "hs_phy_irq",
626 power-domains = <&gcc USB30_PRIM_GDSC>;
638 phy-names = "usb2-phy", "usb3-phy";