Lines Matching +full:phy +full:- +full:bindings
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
29 dma-coherent: true
31 power-domains:
37 A list of phandle and clock-specifier pairs for the clocks
38 listed in clock-names.
40 - description: Master/Core clock, has to be >= 125 MHz
42 - description: Clock source to core during PHY power down.
44 clock-names:
46 - const: bus_clk
47 - const: ref_clk
51 A list of phandles for resets listed in reset-names.
54 - description: USB core reset
55 - description: USB hibernation reset
56 - description: USB APB reset
58 reset-names:
60 - const: usb_crst
61 - const: usb_hibrst
62 - const: usb_apbrst
68 phy-names:
73 - usb2-phy
74 - usb3-phy
76 reset-gpios:
77 description: GPIO used for the reset ulpi-phy
83 "^usb@[0-9a-f]+$":
87 - compatible
88 - reg
89 - "#address-cells"
90 - "#size-cells"
91 - ranges
92 - power-domains
93 - clocks
94 - clock-names
95 - resets
96 - reset-names
101 - |
102 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
103 #include <dt-bindings/power/xlnx-zynqmp-power.h>
104 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
105 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
106 #include <dt-bindings/phy/phy.h>
108 #address-cells = <2>;
109 #size-cells = <2>;
112 #address-cells = <0x2>;
113 #size-cells = <0x2>;
114 compatible = "xlnx,zynqmp-dwc3";
117 clock-names = "bus_clk", "ref_clk";
118 power-domains = <&zynqmp_firmware PD_USB_0>;
122 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
124 phy-names = "usb3-phy";
130 interrupt-names = "host", "otg";
133 dma-coherent;