Lines Matching +full:ufs +full:- +full:ddr
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Universal Flash Storage (UFS) Controller
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,qcs615-ufshc
30 - qcom,qcs8300-ufshc
31 - qcom,sa8775p-ufshc
32 - qcom,sc7180-ufshc
33 - qcom,sc7280-ufshc
34 - qcom,sc8180x-ufshc
35 - qcom,sc8280xp-ufshc
36 - qcom,sdm845-ufshc
37 - qcom,sm6115-ufshc
38 - qcom,sm6125-ufshc
39 - qcom,sm6350-ufshc
40 - qcom,sm8150-ufshc
41 - qcom,sm8250-ufshc
42 - qcom,sm8350-ufshc
43 - qcom,sm8450-ufshc
44 - qcom,sm8550-ufshc
45 - qcom,sm8650-ufshc
46 - qcom,sm8750-ufshc
47 - const: qcom,ufshc
48 - const: jedec,ufs-2.0
54 clock-names:
58 dma-coherent: true
64 interconnect-names:
66 - const: ufs-ddr
67 - const: cpu-ufs
76 phy-names:
78 - const: ufsphy
80 power-domains:
91 reg-names:
93 - const: std
94 - const: ice
96 required-opps:
102 '#reset-cells':
105 reset-names:
107 - const: rst
109 reset-gpios:
112 GPIO connected to the RESET pin of the UFS memory device.
115 - compatible
116 - reg
119 - $ref: ufs-common.yaml
121 - if:
126 - qcom,sc7180-ufshc
132 clock-names:
134 - const: core_clk
135 - const: bus_aggr_clk
136 - const: iface_clk
137 - const: core_clk_unipro
138 - const: ref_clk
139 - const: tx_lane0_sync_clk
140 - const: rx_lane0_sync_clk
143 reg-names:
146 - if:
151 - qcom,msm8998-ufshc
152 - qcom,qcs8300-ufshc
153 - qcom,sa8775p-ufshc
154 - qcom,sc7280-ufshc
155 - qcom,sc8180x-ufshc
156 - qcom,sc8280xp-ufshc
157 - qcom,sm8250-ufshc
158 - qcom,sm8350-ufshc
159 - qcom,sm8450-ufshc
160 - qcom,sm8550-ufshc
161 - qcom,sm8650-ufshc
162 - qcom,sm8750-ufshc
168 clock-names:
170 - const: core_clk
171 - const: bus_aggr_clk
172 - const: iface_clk
173 - const: core_clk_unipro
174 - const: ref_clk
175 - const: tx_lane0_sync_clk
176 - const: rx_lane0_sync_clk
177 - const: rx_lane1_sync_clk
181 reg-names:
184 - if:
189 - qcom,sdm845-ufshc
190 - qcom,sm6350-ufshc
191 - qcom,sm8150-ufshc
197 clock-names:
199 - const: core_clk
200 - const: bus_aggr_clk
201 - const: iface_clk
202 - const: core_clk_unipro
203 - const: ref_clk
204 - const: tx_lane0_sync_clk
205 - const: rx_lane0_sync_clk
206 - const: rx_lane1_sync_clk
207 - const: ice_core_clk
211 reg-names:
214 - reg-names
216 - if:
221 - qcom,msm8996-ufshc
227 clock-names:
229 - const: core_clk
230 - const: bus_clk
231 - const: bus_aggr_clk
232 - const: iface_clk
233 - const: core_clk_unipro
234 - const: core_clk_ice
235 - const: ref_clk
236 - const: tx_lane0_sync_clk
237 - const: rx_lane0_sync_clk
241 reg-names:
244 - if:
249 - qcom,qcs615-ufshc
250 - qcom,sm6115-ufshc
251 - qcom,sm6125-ufshc
257 clock-names:
259 - const: core_clk
260 - const: bus_aggr_clk
261 - const: iface_clk
262 - const: core_clk_unipro
263 - const: ref_clk
264 - const: tx_lane0_sync_clk
265 - const: rx_lane0_sync_clk
266 - const: ice_core_clk
270 reg-names:
273 - reg-names
275 # TODO: define clock bindings for qcom,msm8994-ufshc
277 - if:
279 - qcom,ice
299 - |
300 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
301 #include <dt-bindings/clock/qcom,rpmh.h>
302 #include <dt-bindings/gpio/gpio.h>
303 #include <dt-bindings/interconnect/qcom,sm8450.h>
304 #include <dt-bindings/interrupt-controller/arm-gic.h>
307 #address-cells = <2>;
308 #size-cells = <2>;
310 ufs@1d84000 {
311 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
312 "jedec,ufs-2.0";
316 phy-names = "ufsphy";
317 lanes-per-direction = <2>;
318 #reset-cells = <1>;
320 reset-names = "rst";
321 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
323 vcc-supply = <&vreg_l7b_2p5>;
324 vcc-max-microamp = <1100000>;
325 vccq-supply = <&vreg_l9b_1p2>;
326 vccq-max-microamp = <1200000>;
328 power-domains = <&gcc UFS_PHY_GDSC>;
332 interconnect-names = "ufs-ddr", "cpu-ufs";
334 clock-names = "core_clk",
350 freq-table-hz = <75000000 300000000>,