Lines Matching +full:gcc +full:- +full:sdm845
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,sa8775p-ufshc
30 - qcom,sc7180-ufshc
31 - qcom,sc7280-ufshc
32 - qcom,sc8180x-ufshc
33 - qcom,sc8280xp-ufshc
34 - qcom,sdm845-ufshc
35 - qcom,sm6115-ufshc
36 - qcom,sm6125-ufshc
37 - qcom,sm6350-ufshc
38 - qcom,sm8150-ufshc
39 - qcom,sm8250-ufshc
40 - qcom,sm8350-ufshc
41 - qcom,sm8450-ufshc
42 - qcom,sm8550-ufshc
43 - qcom,sm8650-ufshc
44 - const: qcom,ufshc
45 - const: jedec,ufs-2.0
51 clock-names:
55 dma-coherent: true
61 interconnect-names:
63 - const: ufs-ddr
64 - const: cpu-ufs
73 phy-names:
75 - const: ufsphy
77 power-domains:
88 reg-names:
90 - const: std
91 - const: ice
93 required-opps:
99 '#reset-cells':
102 reset-names:
104 - const: rst
106 reset-gpios:
112 - compatible
113 - reg
116 - $ref: ufs-common.yaml
118 - if:
123 - qcom,sc7180-ufshc
129 clock-names:
131 - const: core_clk
132 - const: bus_aggr_clk
133 - const: iface_clk
134 - const: core_clk_unipro
135 - const: ref_clk
136 - const: tx_lane0_sync_clk
137 - const: rx_lane0_sync_clk
140 reg-names:
143 - if:
148 - qcom,msm8998-ufshc
149 - qcom,sa8775p-ufshc
150 - qcom,sc7280-ufshc
151 - qcom,sc8180x-ufshc
152 - qcom,sc8280xp-ufshc
153 - qcom,sm8250-ufshc
154 - qcom,sm8350-ufshc
155 - qcom,sm8450-ufshc
156 - qcom,sm8550-ufshc
157 - qcom,sm8650-ufshc
163 clock-names:
165 - const: core_clk
166 - const: bus_aggr_clk
167 - const: iface_clk
168 - const: core_clk_unipro
169 - const: ref_clk
170 - const: tx_lane0_sync_clk
171 - const: rx_lane0_sync_clk
172 - const: rx_lane1_sync_clk
176 reg-names:
179 - if:
184 - qcom,sdm845-ufshc
185 - qcom,sm6350-ufshc
186 - qcom,sm8150-ufshc
192 clock-names:
194 - const: core_clk
195 - const: bus_aggr_clk
196 - const: iface_clk
197 - const: core_clk_unipro
198 - const: ref_clk
199 - const: tx_lane0_sync_clk
200 - const: rx_lane0_sync_clk
201 - const: rx_lane1_sync_clk
202 - const: ice_core_clk
206 reg-names:
209 - reg-names
211 - if:
216 - qcom,msm8996-ufshc
222 clock-names:
224 - const: core_clk
225 - const: bus_clk
226 - const: bus_aggr_clk
227 - const: iface_clk
228 - const: core_clk_unipro
229 - const: core_clk_ice
230 - const: ref_clk
231 - const: tx_lane0_sync_clk
232 - const: rx_lane0_sync_clk
236 reg-names:
239 - if:
244 - qcom,sm6115-ufshc
245 - qcom,sm6125-ufshc
251 clock-names:
253 - const: core_clk
254 - const: bus_aggr_clk
255 - const: iface_clk
256 - const: core_clk_unipro
257 - const: ref_clk
258 - const: tx_lane0_sync_clk
259 - const: rx_lane0_sync_clk
260 - const: ice_core_clk
264 reg-names:
267 - reg-names
269 # TODO: define clock bindings for qcom,msm8994-ufshc
271 - if:
273 - qcom,ice
293 - |
294 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
295 #include <dt-bindings/clock/qcom,rpmh.h>
296 #include <dt-bindings/gpio/gpio.h>
297 #include <dt-bindings/interconnect/qcom,sm8450.h>
298 #include <dt-bindings/interrupt-controller/arm-gic.h>
301 #address-cells = <2>;
302 #size-cells = <2>;
305 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
306 "jedec,ufs-2.0";
310 phy-names = "ufsphy";
311 lanes-per-direction = <2>;
312 #reset-cells = <1>;
313 resets = <&gcc GCC_UFS_PHY_BCR>;
314 reset-names = "rst";
315 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
317 vcc-supply = <&vreg_l7b_2p5>;
318 vcc-max-microamp = <1100000>;
319 vccq-supply = <&vreg_l9b_1p2>;
320 vccq-max-microamp = <1200000>;
322 power-domains = <&gcc UFS_PHY_GDSC>;
326 interconnect-names = "ufs-ddr", "cpu-ufs";
328 clock-names = "core_clk",
336 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
337 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
338 <&gcc GCC_UFS_PHY_AHB_CLK>,
339 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
341 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
342 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
343 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
344 freq-table-hz = <75000000 300000000>,