Lines Matching +full:0 +full:x0008004a
20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
90 <0x00000005 0x0000003a>,
91 <0x00000006 0x00000040>,
92 <0x00000007 0x00000044>,
93 <0x00000008 0x0000004a>,
94 <0x00000009 0x0000004f>,
95 <0x0000000a 0x00000054>,
96 <0x00010000 0x0000000d>,
97 <0x00010001 0x00000013>,
98 <0x00010002 0x00000019>,
99 <0x00010003 0x0000001f>,
100 <0x00010004 0x00000025>,
101 <0x00010005 0x0000002d>,
102 <0x00010006 0x00000033>,
103 <0x00010007 0x00000043>,
104 <0x00010008 0x0000004b>,
105 <0x00010009 0x00000053>,
106 <0x00020000 0x00000010>,
107 <0x00020001 0x00000017>,
108 <0x00020002 0x0000001f>,
109 <0x00020003 0x00000029>,
110 <0x00020004 0x00000031>,
111 <0x00020005 0x0000003c>,
112 <0x00020006 0x00000042>,
113 <0x00020007 0x0000004d>,
114 <0x00020008 0x00000056>,
115 <0x00030000 0x00000012>,
116 <0x00030001 0x0000001d>;