Lines Matching +full:0 +full:x5e
19 chip-select lines 0 through 7 respectively.
37 #size-cells = <0>;
38 cell-index = <0>;
39 reg = <0x10600 0x28>;
47 #size-cells = <0>;
48 cell-index = <0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
50 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
51 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
52 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
53 <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
54 <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
55 <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
56 <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
57 <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
64 mode. Here an example for this (SPI controller 0, device 1 and SPI
72 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */
73 <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM */
74 <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */
75 <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>; /* SPI1-DEV2 */