Lines Matching +full:bcm +full:- +full:ns2
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
20 io with 3-byte and 4-byte addressing support.
28 - $ref: spi-controller.yaml#
33 - description: Second Instance of MSPI BRCMSTB SoCs
35 - enum:
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
43 - const: brcm,spi-brcmstb-mspi
44 - description: Second Instance of MSPI BRCMSTB SoCs
46 - enum:
47 - brcm,spi-brcmstb-qspi
48 - brcm,spi-brcmstb-mspi
49 - brcm,spi-nsp-qspi
50 - brcm,spi-ns2-qspi
51 - const: brcm,spi-bcm-qspi
57 reg-names:
60 - const: mspi
61 - const: bspi
62 - enum: [ intr_regs, intr_status_reg, cs_reg ]
63 - enum: [ intr_regs, intr_status_reg, cs_reg ]
64 - enum: [ intr_regs, intr_status_reg, cs_reg ]
70 interrupt-names:
72 - minItems: 1
74 - const: mspi_done
75 - const: mspi_halted
76 - const: spi_lr_fullness_reached
77 - const: spi_lr_session_aborted
78 - const: spi_lr_impatient
79 - const: spi_lr_session_done
80 - const: spi_lr_overread
81 - const: spi_l1_intr
87 native-endian:
94 - reg
95 - reg-names
96 - interrupts
97 - interrupt-names
100 - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
102 compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
104 reg-names = "mspi", "bspi", "cs_reg";
106 interrupt-parent = <&gic>;
107 interrupt-names = "mspi_done",
115 #address-cells = <0x1>;
116 #size-cells = <0x0>;
119 #size-cells = <0x2>;
120 #address-cells = <0x2>;
123 spi-max-frequency = <0x2625a00>;
124 spi-cpol;
125 spi-cpha;
128 - | # BRCMSTB SoC: MSPI master for any SPI device
131 compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
133 reg-names = "mspi";
135 interrupt-parent = <&irq0_aon_intc>;
136 interrupt-names = "mspi_done";
137 #address-cells = <1>;
138 #size-cells = <0>;
140 - | # iProc SoC
141 #include <dt-bindings/interrupt-controller/irq.h>
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
150 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
158 interrupt-names = "mspi_done",
165 num-cs = <2>;
166 #address-cells = <1>;
167 #size-cells = <0>;
169 - | # NS2 SoC
170 #include <dt-bindings/interrupt-controller/irq.h>
171 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
179 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
181 interrupt-names = "spi_l1_intr";
183 num-cs = <2>;
184 #address-cells = <1>;
185 #size-cells = <0>;
188 #address-cells = <1>;
189 #size-cells = <1>;
192 spi-max-frequency = <12500000>;
193 spi-cpol;
194 spi-cpha;