Lines Matching +full:channel +full:- +full:7
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
37 reset-gpios:
42 areg-supply:
47 ti,mic-bias-source:
50 0 - Mic bias is set to VREF
51 1 - Mic bias is set to VREF × 1.096
52 6 - Mic bias is set to AVDD
56 ti,vref-source:
59 0 - Set VREF to 2.75V
60 1 - Set VREF to 2.5V
61 2 - Set VREF to 1.375V
65 ti,pdm-edge-select:
70 0 - (default) Odd channel is latched on the negative edge and even
71 channel is latched on the positive edge.
72 1 - Odd channel is latched on the positive edge and even channel is
75 PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
76 PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
77 PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
78 PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
80 $ref: /schemas/types.yaml#/definitions/uint32-array
87 ti,gpi-config:
92 0 - (default) disabled
93 1 - GPIX is configured as a general-purpose input (GPI)
94 2 - GPIX is configured as a master clock input (MCLK)
95 3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
96 4 - GPIX is configured as a PDM data input for channel 1 and channel
98 5 - GPIX is configured as a PDM data input for channel 3 and channel
100 6 - GPIX is configured as a PDM data input for channel 5 and channel
102 7 - GPIX is configured as a PDM data input for channel 7 and channel
105 $ref: /schemas/types.yaml#/definitions/uint32-array
109 maximum: 7
112 ti,gpio-config:
120 0 - disabled
121 1 - GPIO1 is configured as a general-purpose output (GPO)
122 2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
123 3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
124 4 - GPIO1 is configured as a PDM clock output (PDMCLK)
125 8 - GPIO1 is configured as an input to control when MICBIAS turns on or
127 9 - GPIO1 is configured as a general-purpose input (GPI)
128 10 - GPIO1 is configured as a master clock input (MCLK)
129 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
130 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
132 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
134 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
136 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
140 0 - Hi-Z output
141 1 - Drive active low and active high
142 2 - (default) Drive active low and weak high
143 3 - Drive active low and Hi-Z
144 4 - Drive weak low and active high
145 5 - Drive Hi-Z and active high
147 $ref: /schemas/types.yaml#/definitions/uint32-array
154 ti,asi-tx-drive:
157 When set the device will set the Tx ASI output to a Hi-Z state for unused
161 '^ti,gpo-config-[1-4]$':
162 $ref: /schemas/types.yaml#/definitions/uint32-array
171 0 - (default) disabled
172 1 - GPOX is configured as a general-purpose output (GPO)
173 2 - GPOX is configured as a device interrupt output (IRQ)
174 3 - GPOX is configured as a secondary ASI output (SDOUT2)
175 4 - GPOX is configured as a PDM clock output (PDMCLK)
179 0d - (default) Hi-Z output
180 1d - Drive active low and active high
181 2d - Drive active low and weak high
182 3d - Drive active low and Hi-Z
183 4d - Drive weak low and active high
184 5d - Drive Hi-Z and active high
187 - compatible
188 - reg
193 - |
194 #include <dt-bindings/gpio/gpio.h>
196 #address-cells = <1>;
197 #size-cells = <0>;
201 ti,mic-bias-source = <6>;
202 ti,pdm-edge-select = <0 1 0 1>;
203 ti,gpi-config = <4 5 6 7>;
204 ti,gpio-config = <10 2>;
205 ti,gpo-config-1 = <0 0>;
206 ti,gpo-config-2 = <0 0>;
207 reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;