Lines Matching +full:48 +full:khz

23   In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24   for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25   44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30   Clocking setup for 48KHz family:
37   Clocking setup for 44.1KHz family:
76       - description: Parent for CPB_McASP auxclk (for 48KHz)
77       - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79       - description: Parent for CPB_SCKI clock (for 48KHz)
80       - description: Parent for CPB_SCKI clock (for 44.1KHz)
82       - description: Parent for IVI_McASP auxclk (for 48KHz)
83       - description: Parent for IVI_McASP auxclk (for 44.1KHz)
85       - description: Parent for IVI_SCKI clock (for 48KHz)
86       - description: Parent for IVI_SCKI clock (for 44.1KHz)