Lines Matching +full:playback +full:- +full:only
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
24 "fsl,mpc8610-dma-channel") can remain. If these nodes are left as
25 "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
32 - items:
33 - enum:
34 - fsl,imx50-ssi
35 - fsl,imx53-ssi
36 - const: fsl,imx51-ssi
37 - const: fsl,imx21-ssi
38 - items:
39 - enum:
40 - fsl,imx25-ssi
41 - fsl,imx27-ssi
42 - fsl,imx35-ssi
43 - fsl,imx51-ssi
44 - const: fsl,imx21-ssi
45 - items:
46 - enum:
47 - fsl,imx6q-ssi
48 - fsl,imx6sl-ssi
49 - fsl,imx6sx-ssi
50 - const: fsl,imx51-ssi
51 - items:
52 - const: fsl,imx21-ssi
53 - items:
54 - const: fsl,mpc8610-ssi
64 - description: The ipg clock for register access
65 - description: clock for SSI master mode
68 clock-names:
70 - const: ipg
71 - const: baud
76 - items:
77 - description: DMA controller phandle and request line for RX
78 - description: DMA controller phandle and request line for TX
79 - items:
80 - description: DMA controller phandle and request line for RX0
81 - description: DMA controller phandle and request line for TX0
82 - description: DMA controller phandle and request line for RX1
83 - description: DMA controller phandle and request line for TX1
85 dma-names:
87 - items:
88 - const: rx
89 - const: tx
90 - items:
91 - const: rx0
92 - const: tx0
93 - const: rx1
94 - const: tx1
96 "#sound-dai-cells":
100 cell-index:
105 ac97-gpios:
106 $ref: /schemas/types.yaml#/definitions/phandle-array
107 description: Please refer to soc-ac97link.txt
109 codec-handle:
116 fsl,fifo-depth:
123 fsl,fiq-stream-filter:
132 enum: [ ac97-slave, ac97-master, i2s-slave, i2s-master,
133 lj-slave, lj-master, rj-slave, rj-master ]
135 "ac97-slave" - AC97 mode, SSI is clock slave
136 "ac97-master" - AC97 mode, SSI is clock master
137 "i2s-slave" - I2S mode, SSI is clock slave
138 "i2s-master" - I2S mode, SSI is clock master
139 "lj-slave" - Left justified mode, SSI is clock slave
140 "lj-master" - Left justified mode, SSI is clock master
141 "rj-slave" - Right justified mode, SSI is clock slave
142 "rj-master" - Right justified mode, SSI is clock master
144 fsl,ssi-asynchronous:
150 playback and capture to use different sample sizes and
156 fsl,playback-dma:
159 playback of audio. This is typically dictated by SOC
160 design. Only used on Power Architecture.
162 fsl,capture-dma:
166 by SOC design. Only used on Power Architecture.
169 - compatible
170 - reg
171 - interrupts
172 - fsl,fifo-depth
175 - $ref: dai-common.yaml#
180 - |
181 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/imx6qdl-clock.h>
184 compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi";
189 clock-names = "ipg", "baud";
191 dma-names = "rx", "tx";
192 #sound-dai-cells = <0>;
193 fsl,fifo-depth = <15>;