Lines Matching +full:detect +full:- +full:us
3 DA7218 is an audio codec with HP detect feature.
8 - compatible : Should be "dlg,da7217" or "dlg,da7218"
9 - reg: Specifies the I2C slave address
11 - VDD-supply: VDD power supply for the device
12 - VDDMIC-supply: VDDMIC power supply for the device
13 - VDDIO-supply: VDDIO power supply for the device
18 - interrupts: IRQ line info for DA7218 chip.
19 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
21 - interrupt-names : Name associated with interrupt line. Should be "wakeup" if
23 - wakeup-source: Flag to indicate this device can wake system (suspend/resume).
25 - clocks : phandle and clock specifier for codec MCLK.
26 - clock-names : Clock name string for 'clocks' attribute, should be "mclk".
28 - dlg,micbias1-lvl-millivolt : Voltage (mV) for Mic Bias 1
30 - dlg,micbias2-lvl-millivolt : Voltage (mV) for Mic Bias 2
32 - dlg,mic1-amp-in-sel : Mic1 input source type
34 - dlg,mic2-amp-in-sel : Mic2 input source type
36 - dlg,dmic1-data-sel : DMIC1 channel select based on clock edge.
38 - dlg,dmic1-samplephase : When to sample audio from DMIC1.
40 - dlg,dmic1-clkrate-hz : DMic1 clock frequency (Hz).
42 - dlg,dmic2-data-sel : DMic2 channel select based on clock edge.
44 - dlg,dmic2-samplephase : When to sample audio from DMic2.
46 - dlg,dmic2-clkrate-hz : DMic2 clock frequency (Hz).
48 - dlg,hp-diff-single-supply : Boolean flag, use single supply for HP
53 Optional Child node - 'da7218_hpldet' (DA7218 only):
56 - dlg,jack-rate-us : Time between jack detect measurements (us)
58 - dlg,jack-debounce : Number of debounce measurements taken for jack detect
60 - dlg,jack-threshold-pct : Threshold level for jack detection (% of VDD)
62 - dlg,comp-inv : Boolean flag, invert comparator output
63 - dlg,hyst : Boolean flag, enable hysteresis
64 - dlg,discharge : Boolean flag, auto discharge of Mic Bias on jack removal
73 interrupt-parent = <&gpio6>;
75 wakeup-source;
77 VDD-supply = <®_audio>;
78 VDDMIC-supply = <®_audio>;
79 VDDIO-supply = <®_audio>;
82 clock-names = "mclk";
84 dlg,micbias1-lvl-millivolt = <2600>;
85 dlg,micbias2-lvl-millivolt = <2600>;
86 dlg,mic1-amp-in-sel = "diff";
87 dlg,mic2-amp-in-sel = "diff";
89 dlg,dmic1-data-sel = "lrise_rfall";
90 dlg,dmic1-samplephase = "on_clkedge";
91 dlg,dmic1-clkrate-hz = <3000000>;
92 dlg,dmic2-data-sel = "lrise_rfall";
93 dlg,dmic2-samplephase = "on_clkedge";
94 dlg,dmic2-clkrate-hz = <3000000>;
97 dlg,jack-rate-us = <40>;
98 dlg,jack-debounce = <2>;
99 dlg,jack-threshold-pct = <84>;