Lines Matching +full:0 +full:x32000
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
171 const: 0
185 const: 0
219 const: 0
327 "^(pru|rtu|txpru)@[0-9a-f]+$":
380 pruss: pruss@0 {
382 reg = <0x0 0x80000>;
387 pruss_mem: memories@0 {
388 reg = <0x0 0x2000>,
389 <0x2000 0x2000>,
390 <0x10000 0x3000>;
398 reg = <0x26000 0x2000>;
399 ranges = <0x00 0x26000 0x2000>;
403 #size-cells = <0>;
406 reg = <0x30>;
407 #clock-cells = <0>;
416 reg = <0x32000 0x58>;
421 reg = <0x20000 0x2000>;
433 reg = <0x34000 0x2000>,
434 <0x22000 0x400>,
435 <0x22400 0x100>;
442 reg = <0x38000 0x2000>,
443 <0x24000 0x400>,
444 <0x24400 0x100>;
451 reg = <0x32400 0x90>;
456 #size-cells = <0>;
464 pruss1: pruss@0 {
466 reg = <0x0 0x40000>;
471 pruss1_mem: memories@0 {
472 reg = <0x0 0x2000>,
473 <0x2000 0x2000>,
474 <0x10000 0x8000>;
482 reg = <0x26000 0x2000>;
483 ranges = <0x00 0x26000 0x2000>;
487 #size-cells = <0>;
490 reg = <0x30>;
491 #clock-cells = <0>;
500 reg = <0x32000 0x58>;
505 reg = <0x20000 0x2000>;
519 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
524 reg = <0x34000 0x3000>,
525 <0x22000 0x400>,
526 <0x22400 0x100>;
533 reg = <0x38000 0x3000>,
534 <0x24000 0x400>,
535 <0x24400 0x100>;
542 reg = <0x32400 0x90>;
547 #size-cells = <0>;