Lines Matching +full:set +full:- +full:gpios
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
21 - required:
22 - aspeed,sirq-polarity-sense
26 const: aspeed,ast2500-vuart
27 - if:
30 const: mrvl,mmp-uart
33 reg-shift:
36 - reg-shift
37 - if:
42 - enum:
43 - ns8250
44 - ns16450
45 - ns16550
46 - ns16550a
49 - required: [ clock-frequency ]
50 - required: [ clocks ]
52 - if:
56 const: nxp,lpc1850-uart
59 clock-names:
61 - const: uartclk
62 - const: reg
65 clock-names:
67 - const: core
68 - const: bus
73 - const: ns8250
74 - const: ns16450
75 - const: ns16550
76 - const: ns16550a
77 - const: ns16850
78 - const: aspeed,ast2400-vuart
79 - const: aspeed,ast2500-vuart
80 - const: intel,xscale-uart
81 - const: mrvl,pxa-uart
82 - const: nuvoton,wpcm450-uart
83 - const: nuvoton,npcm750-uart
84 - const: nvidia,tegra20-uart
85 - const: nxp,lpc3220-uart
86 - items:
87 - enum:
88 - exar,xr16l2552
89 - exar,xr16l2551
90 - exar,xr16l2550
91 - const: ns8250
92 - items:
93 - enum:
94 - altr,16550-FIFO32
95 - altr,16550-FIFO64
96 - altr,16550-FIFO128
97 - fsl,16550-FIFO64
98 - andestech,uart16550
99 - nxp,lpc1850-uart
100 - opencores,uart16550-rtlsvn105
101 - ti,da830-uart
102 - const: ns16550a
103 - items:
104 - enum:
105 - ns16750
106 - fsl,ns16550
107 - cavium,octeon-3860-uart
108 - xlnx,xps-uart16550-2.00.b
109 - ralink,rt2880-uart
110 - enum:
111 - ns16550 # Deprecated, unless the FIFO really is broken
112 - ns16550a
113 - items:
114 - enum:
115 - nuvoton,npcm845-uart
116 - const: nuvoton,npcm750-uart
117 - items:
118 - enum:
119 - ralink,mt7620a-uart
120 - ralink,rt3052-uart
121 - ralink,rt3883-uart
122 - const: ralink,rt2880-uart
123 - enum:
124 - ns16550 # Deprecated, unless the FIFO really is broken
125 - ns16550a
126 - items:
127 - enum:
128 - mediatek,mt7622-btif
129 - mediatek,mt7623-btif
130 - const: mediatek,mtk-btif
131 - items:
132 - enum:
133 - mrvl,mmp-uart
134 - spacemit,k1-uart
135 - const: intel,xscale-uart
136 - items:
137 - enum:
138 - nvidia,tegra30-uart
139 - nvidia,tegra114-uart
140 - nvidia,tegra124-uart
141 - nvidia,tegra210-uart
142 - nvidia,tegra186-uart
143 - nvidia,tegra194-uart
144 - nvidia,tegra234-uart
145 - const: nvidia,tegra20-uart
153 clock-frequency: true
158 - description: The core function clock
159 - description: An optional bus clock
161 clock-names:
165 - items:
166 - const: core
167 - const: bus
168 - items:
169 - const: uartclk
170 - const: reg
176 dma-names:
183 current-speed:
187 reg-offset:
192 reg-shift:
195 reg-io-width:
198 device. There are some systems that require 32-bit accesses to the
201 used-by-rtas:
204 Set to indicate that the port is in use by the OpenFirmware RTAS and
207 no-loopback-test:
210 Set to indicate that the port does not implement loopback test mode.
212 fifo-size:
216 auto-flow-control:
223 tx-threshold:
228 overrun-throttle-ms:
232 rts-gpios: true
233 cts-gpios: true
234 dtr-gpios: true
235 dsr-gpios: true
236 rng-gpios: true
237 dcd-gpios: true
239 aspeed,sirq-polarity-sense:
240 $ref: /schemas/types.yaml#/definitions/phandle-array
242 Phandle to aspeed,ast2500-scu compatible syscon alongside register
245 applicable to aspeed,ast2500-vuart.
248 aspeed,lpc-io-reg:
249 $ref: /schemas/types.yaml#/definitions/uint32-array
252 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
254 aspeed,lpc-interrupts:
255 $ref: /schemas/types.yaml#/definitions/uint32-array
259 A 2-cell property describing the VUART SIRQ number and SIRQ
261 applicable to aspeed,ast2500-vuart.
264 - reg
265 - interrupts
272 - spacemit,k1-uart
273 - nxp,lpc1850-uart
276 - clocks
277 - clock-names
281 clock-names:
287 clock-names:
293 - |
298 reg-shift = <2>;
299 clock-frequency = <48000000>;
301 - |
302 #include <dt-bindings/gpio/gpio.h>
307 clock-frequency = <48000000>;
308 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
309 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
310 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
311 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
312 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
313 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
315 - |
316 #include <dt-bindings/clock/aspeed-clock.h>
317 #include <dt-bindings/interrupt-controller/irq.h>
319 compatible = "aspeed,ast2500-vuart";
321 reg-shift = <2>;
324 no-loopback-test;
325 aspeed,lpc-io-reg = <0x3f8>;
326 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;