Lines Matching +full:octeon +full:- +full:3860 +full:- +full:gpio
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
21 - required:
22 - aspeed,sirq-polarity-sense
26 const: aspeed,ast2500-vuart
27 - if:
30 const: mrvl,mmp-uart
33 reg-shift:
36 - reg-shift
37 - if:
42 - enum:
43 - ns8250
44 - ns16450
45 - ns16550
46 - ns16550a
49 - required: [ clock-frequency ]
50 - required: [ clocks ]
51 - if:
55 const: nxp,lpc1850-uart
58 clock-names:
60 - const: uartclk
61 - const: reg
62 - if:
66 const: spacemit,k1-uart
69 clock-names:
71 - const: core
72 - const: bus
73 - if:
78 - spacemit,k1-uart
79 - nxp,lpc1850-uart
82 - clocks
83 - clock-names
87 clock-names:
93 clock-names:
99 - const: ns8250
100 - const: ns16450
101 - const: ns16550
102 - const: ns16550a
103 - const: ns16850
104 - const: aspeed,ast2400-vuart
105 - const: aspeed,ast2500-vuart
106 - const: intel,xscale-uart
107 - const: mrvl,pxa-uart
108 - const: nuvoton,wpcm450-uart
109 - const: nuvoton,npcm750-uart
110 - const: nvidia,tegra20-uart
111 - const: nxp,lpc3220-uart
112 - items:
113 - enum:
114 - exar,xr16l2552
115 - exar,xr16l2551
116 - exar,xr16l2550
117 - const: ns8250
118 - items:
119 - enum:
120 - altr,16550-FIFO32
121 - altr,16550-FIFO64
122 - altr,16550-FIFO128
123 - fsl,16550-FIFO64
124 - andestech,uart16550
125 - nxp,lpc1850-uart
126 - opencores,uart16550-rtlsvn105
127 - ti,da830-uart
128 - const: ns16550a
129 - items:
130 - enum:
131 - ns16750
132 - fsl,ns16550
133 - cavium,octeon-3860-uart
134 - xlnx,xps-uart16550-2.00.b
135 - ralink,rt2880-uart
136 - enum:
137 - ns16550 # Deprecated, unless the FIFO really is broken
138 - ns16550a
139 - items:
140 - enum:
141 - nuvoton,npcm845-uart
142 - const: nuvoton,npcm750-uart
143 - items:
144 - enum:
145 - ralink,mt7620a-uart
146 - ralink,rt3052-uart
147 - ralink,rt3883-uart
148 - const: ralink,rt2880-uart
149 - enum:
150 - ns16550 # Deprecated, unless the FIFO really is broken
151 - ns16550a
152 - items:
153 - enum:
154 - mediatek,mt7622-btif
155 - mediatek,mt7623-btif
156 - const: mediatek,mtk-btif
157 - items:
158 - enum:
159 - mrvl,mmp-uart
160 - spacemit,k1-uart
161 - const: intel,xscale-uart
162 - items:
163 - enum:
164 - nvidia,tegra30-uart
165 - nvidia,tegra114-uart
166 - nvidia,tegra124-uart
167 - nvidia,tegra210-uart
168 - nvidia,tegra186-uart
169 - nvidia,tegra194-uart
170 - nvidia,tegra234-uart
171 - const: nvidia,tegra20-uart
179 clock-frequency: true
184 - description: The core function clock
185 - description: An optional bus clock
187 clock-names:
191 - enum:
192 - main
193 - uart
194 - items:
195 - const: core
196 - const: bus
197 - items:
198 - const: uartclk
199 - const: reg
205 dma-names:
212 current-speed:
216 reg-offset:
221 reg-shift:
224 reg-io-width:
227 device. There are some systems that require 32-bit accesses to the
230 used-by-rtas:
236 no-loopback-test:
241 fifo-size:
245 auto-flow-control:
252 tx-threshold:
257 overrun-throttle-ms:
261 rts-gpios: true
262 cts-gpios: true
263 dtr-gpios: true
264 dsr-gpios: true
265 rng-gpios: true
266 dcd-gpios: true
268 aspeed,sirq-polarity-sense:
269 $ref: /schemas/types.yaml#/definitions/phandle-array
271 Phandle to aspeed,ast2500-scu compatible syscon alongside register
274 applicable to aspeed,ast2500-vuart.
277 aspeed,lpc-io-reg:
278 $ref: /schemas/types.yaml#/definitions/uint32-array
281 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
283 aspeed,lpc-interrupts:
284 $ref: /schemas/types.yaml#/definitions/uint32-array
288 A 2-cell property describing the VUART SIRQ number and SIRQ
290 applicable to aspeed,ast2500-vuart.
293 - reg
294 - interrupts
299 - |
304 reg-shift = <2>;
305 clock-frequency = <48000000>;
307 - |
308 #include <dt-bindings/gpio/gpio.h>
313 clock-frequency = <48000000>;
314 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
315 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
316 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
317 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
318 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
319 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
321 - |
322 #include <dt-bindings/clock/aspeed-clock.h>
323 #include <dt-bindings/interrupt-controller/irq.h>
325 compatible = "aspeed,ast2500-vuart";
327 reg-shift = <2>;
330 no-loopback-test;
331 aspeed,lpc-io-reg = <0x3f8>;
332 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;