Lines Matching +full:npcm750 +full:- +full:memory +full:- +full:controller
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
21 - required:
22 - aspeed,sirq-polarity-sense
26 const: aspeed,ast2500-vuart
27 - if:
30 const: mrvl,mmp-uart
33 reg-shift:
36 - reg-shift
37 - if:
42 - enum:
43 - ns8250
44 - ns16450
45 - ns16550
46 - ns16550a
49 - required: [ clock-frequency ]
50 - required: [ clocks ]
55 - const: ns8250
56 - const: ns16450
57 - const: ns16550
58 - const: ns16550a
59 - const: ns16850
60 - const: aspeed,ast2400-vuart
61 - const: aspeed,ast2500-vuart
62 - const: intel,xscale-uart
63 - const: mrvl,pxa-uart
64 - const: nuvoton,wpcm450-uart
65 - const: nuvoton,npcm750-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
68 - items:
69 - enum:
70 - exar,xr16l2552
71 - exar,xr16l2551
72 - exar,xr16l2550
73 - const: ns8250
74 - items:
75 - enum:
76 - altr,16550-FIFO32
77 - altr,16550-FIFO64
78 - altr,16550-FIFO128
79 - fsl,16550-FIFO64
80 - fsl,ns16550
81 - andestech,uart16550
82 - nxp,lpc1850-uart
83 - opencores,uart16550-rtlsvn105
84 - ti,da830-uart
85 - const: ns16550a
86 - items:
87 - enum:
88 - ns16750
89 - cavium,octeon-3860-uart
90 - xlnx,xps-uart16550-2.00.b
91 - ralink,rt2880-uart
92 - enum:
93 - ns16550 # Deprecated, unless the FIFO really is broken
94 - ns16550a
95 - items:
96 - enum:
97 - nuvoton,npcm845-uart
98 - const: nuvoton,npcm750-uart
99 - items:
100 - enum:
101 - ralink,mt7620a-uart
102 - ralink,rt3052-uart
103 - ralink,rt3883-uart
104 - const: ralink,rt2880-uart
105 - enum:
106 - ns16550 # Deprecated, unless the FIFO really is broken
107 - ns16550a
108 - items:
109 - enum:
110 - mediatek,mt7622-btif
111 - mediatek,mt7623-btif
112 - const: mediatek,mtk-btif
113 - items:
114 - const: mrvl,mmp-uart
115 - const: intel,xscale-uart
116 - items:
117 - enum:
118 - nvidia,tegra30-uart
119 - nvidia,tegra114-uart
120 - nvidia,tegra124-uart
121 - nvidia,tegra210-uart
122 - nvidia,tegra186-uart
123 - nvidia,tegra194-uart
124 - nvidia,tegra234-uart
125 - const: nvidia,tegra20-uart
133 clock-frequency: true
141 current-speed:
145 reg-offset:
150 reg-shift:
153 reg-io-width:
156 device. There are some systems that require 32-bit accesses to the
159 used-by-rtas:
165 no-loopback-test:
170 fifo-size:
174 auto-flow-control:
181 tx-threshold:
186 overrun-throttle-ms:
190 rts-gpios: true
191 cts-gpios: true
192 dtr-gpios: true
193 dsr-gpios: true
194 rng-gpios: true
195 dcd-gpios: true
197 aspeed,sirq-polarity-sense:
198 $ref: /schemas/types.yaml#/definitions/phandle-array
200 Phandle to aspeed,ast2500-scu compatible syscon alongside register
203 applicable to aspeed,ast2500-vuart.
206 aspeed,lpc-io-reg:
207 $ref: /schemas/types.yaml#/definitions/uint32-array
210 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
212 aspeed,lpc-interrupts:
213 $ref: /schemas/types.yaml#/definitions/uint32-array
217 A 2-cell property describing the VUART SIRQ number and SIRQ
219 applicable to aspeed,ast2500-vuart.
222 - reg
223 - interrupts
228 - |
233 reg-shift = <2>;
234 clock-frequency = <48000000>;
236 - |
237 #include <dt-bindings/gpio/gpio.h>
242 clock-frequency = <48000000>;
243 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
244 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
245 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
246 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
247 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
248 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
250 - |
251 #include <dt-bindings/clock/aspeed-clock.h>
252 #include <dt-bindings/interrupt-controller/irq.h>
254 compatible = "aspeed,ast2500-vuart";
256 reg-shift = <2>;
259 no-loopback-test;
260 aspeed,lpc-io-reg = <0x3f8>;
261 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;