Lines Matching +full:riscv +full:- +full:j +full:- +full:extension
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
19 given extension.
21 Once a standard extension has been ratified, no changes in behaviour can be
22 made without the creation of a new extension.
31 const: riscv
34 riscv,isa:
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from
39 https://riscv.org/specifications/
43 Notably, riscv,isa was defined prior to the creation of the
48 insensitive, letters in the riscv,isa string must be all
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
54 riscv,isa-base:
59 - rv32i
60 - rv64i
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/string-array
69 - const: i
78 - const: m
80 The standard M extension for integer multiplication and division, as
84 - const: a
86 The standard A extension for atomic instructions, as ratified in the
89 - const: f
91 The standard F extension for single-precision floating point, as
95 - const: d
97 The standard D extension for double-precision floating-point, as
101 - const: q
103 The standard Q extension for quad-precision floating-point, as
107 - const: c
109 The standard C extension for compressed instructions, as ratified in
112 - const: v
114 The standard V extension for vector operations, as ratified
115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec.
118 - const: h
120 The standard H extension for hypervisors as ratified in the 20191213
123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia
126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine-mode-visible csr and behavioural
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
131 - const: smmpm
133 The standard Smmpm extension for M-mode pointer masking as
135 of riscv-j-extension.
137 - const: smnpm
139 The standard Smnpm extension for next-mode pointer masking as
141 of riscv-j-extension.
143 - const: smstateen
145 The standard Smstateen extension for controlling access to CSRs
146 added by other RISC-V extensions in H/S/VS/U/VU modes and as
147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
149 - const: ssaia
151 The standard Ssaia supervisor-level extension for the advanced
152 interrupt architecture for supervisor-mode-visible csr and
154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
156 - const: sscofpmf
158 The standard Sscofpmf supervisor-level extension for count overflow
159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
160 to manually trigger workflow. (#2)") of riscv-count-overflow.
162 - const: ssnpm
164 The standard Ssnpm extension for next-mode pointer masking as
166 of riscv-j-extension.
168 - const: sstc
170 The standard Sstc supervisor-level extension for time compare as
172 workflow. (#2)") of riscv-time-compare.
174 - const: svade
176 The standard Svade supervisor-level extension for SW-managed PTE A/D
192 Svadu turned-off at boot time. To use Svadu, supervisor must
193 explicitly enable it using the SBI FWFT extension.
195 - const: svadu
197 The standard Svadu supervisor-level extension for hardware updating
199 privileged ISA specification. Please refer to Svade dt-binding
202 - const: svinval
204 The standard Svinval supervisor-level extension for fine-grained
205 address-translation cache invalidation as ratified in the 20191213
208 - const: svnapot
210 The standard Svnapot supervisor-level extensions for napot
214 - const: svpbmt
216 The standard Svpbmt supervisor-level extensions for page-based
220 - const: svvptc
222 The standard Svvptc supervisor-level extension for
223 address-translation cache behaviour with respect to invalid entries
225 riscv-svvptc.
227 - const: zabha
229 The Zabha extension for Byte and Halfword Atomic Memory Operations
231 riscv-zabha.
233 - const: zacas
235 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
237 ratified") of the riscv-zacas.
239 - const: zawrs
241 The Zawrs extension for entering a low-power state or for trapping
244 riscv/zawrs") of riscv-isa-manual.
246 - const: zba
248 The standard Zba bit-manipulation extension for address generation
250 request #158 from hirooih/clmul-fix-loop-end-condition") of
251 riscv-bitmanip.
253 - const: zbb
255 The standard Zbb bit-manipulation extension for basic bit-manipulation
257 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
259 - const: zbc
261 The standard Zbc bit-manipulation extension for carry-less
263 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
265 - const: zbkb
268 in version 1.0 of RISC-V Cryptography Extensions Volume I
271 - const: zbkc
273 The standard Zbkc carry-less multiply instructions as ratified
274 in version 1.0 of RISC-V Cryptography Extensions Volume I
277 - const: zbkx
280 in version 1.0 of RISC-V Cryptography Extensions Volume I
283 - const: zbs
285 The standard Zbs bit-manipulation extension for single-bit
287 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
289 - const: zca
291 The Zca extension part of Zc* standard extensions for code size
293 RV64 as it contains no instructions") of riscv-code-size-reduction,
294 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
297 - const: zcb
299 The Zcb extension part of Zc* standard extensions for code size
301 RV64 as it contains no instructions") of riscv-code-size-reduction,
302 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
305 - const: zcd
307 The Zcd extension part of Zc* standard extensions for code size
309 RV64 as it contains no instructions") of riscv-code-size-reduction,
310 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
313 - const: zcf
315 The Zcf extension part of Zc* standard extensions for code size
317 RV64 as it contains no instructions") of riscv-code-size-reduction,
318 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
321 - const: zcmop
323 The standard Zcmop extension version 1.0, as ratified in commit
324 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
326 - const: zfa
328 The standard Zfa extension for additional floating point
330 riscv-isa-manual.
332 - const: zfh
334 The standard Zfh extension for 16-bit half-precision binary
335 floating-point instructions, as ratified in commit 64074bc ("Update
336 version numbers for Zfh/Zfinx") of riscv-isa-manual.
338 - const: zfhmin
340 The standard Zfhmin extension which provides minimal support for
341 16-bit half-precision binary floating-point instructions, as ratified
343 riscv-isa-manual.
345 - const: ziccrse
347 The standard Ziccrse extension which provides forward progress
349 ("Updated to ratified state.") of the riscv profiles specification.
351 - const: zk
353 The standard Zk Standard Scalar cryptography extension as ratified
354 in version 1.0 of RISC-V Cryptography Extensions Volume I
357 - const: zkn
360 version 1.0 of RISC-V Cryptography Extensions Volume I
363 - const: zknd
366 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
369 - const: zkne
372 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
375 - const: zknh
378 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
381 - const: zkr
383 The standard Zkr entropy source extension as ratified in version
384 1.0 of RISC-V Cryptography Extensions Volume I specification.
386 extension is accessible at the privilege level to which that
387 device-tree has been provided.
389 - const: zks
392 version 1.0 of RISC-V Cryptography Extensions Volume I
395 - const: zksed
398 as ratified in version 1.0 of RISC-V Cryptography Extensions
401 - const: zksh
404 as ratified in version 1.0 of RISC-V Cryptography Extensions
407 - const: zkt
410 in version 1.0 of RISC-V Cryptography Extensions Volume I
413 - const: zicbom
415 The standard Zicbom extension for base cache management operations as
416 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
418 - const: zicbop
420 The standard Zicbop extension for cache-block prefetch instructions
421 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
422 riscv-CMOs.
424 - const: zicboz
426 The standard Zicboz extension for cache-block zeroing as ratified
427 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
429 - const: zicntr
431 The standard Zicntr extension for base counters and timers, as
435 - const: zicond
437 The standard Zicond extension for conditional arithmetic and
438 conditional-select/move operations as ratified in commit 95cf1f9
439 ("Add changes requested by Ved during signoff") of riscv-zicond.
441 - const: zicsr
443 The standard Zicsr extension for control and status register
448 special case read-only CSRs, that were moved into the Zicntr and
452 - const: zifencei
454 The standard Zifencei extension for instruction-fetch fence, as
458 - const: zihintpause
460 The standard Zihintpause extension for pause hints, as ratified in
461 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
463 - const: zihintntl
465 The standard Zihintntl extension for non-temporal locality hints, as
467 riscv-isa-manual.
469 - const: zihpm
471 The standard Zihpm extension for hardware performance counters, as
475 - const: zimop
477 The standard Zimop extension version 1.0, as ratified in commit
478 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
480 - const: ztso
482 The standard Ztso extension for total store ordering, as ratified
484 riscv-isa-manual.
486 - const: zvbb
488 The standard Zvbb extension for vectored basic bit-manipulation
490 riscv-crypto-spec-vector.adoc") of riscv-crypto.
492 - const: zvbc
494 The standard Zvbc extension for vectored carryless multiplication
496 riscv-crypto-spec-vector.adoc") of riscv-crypto.
498 - const: zve32f
500 The standard Zve32f extension for embedded processors, as ratified
502 riscv-v-spec.
504 - const: zve32x
506 The standard Zve32x extension for embedded processors, as ratified
508 riscv-v-spec.
510 - const: zve64d
512 The standard Zve64d extension for embedded processors, as ratified
514 riscv-v-spec.
516 - const: zve64f
518 The standard Zve64f extension for embedded processors, as ratified
520 riscv-v-spec.
522 - const: zve64x
524 The standard Zve64x extension for embedded processors, as ratified
526 riscv-v-spec.
528 - const: zvfh
530 The standard Zvfh extension for vectored half-precision
531 floating-point instructions, as ratified in commit e2ccd05
532 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
534 - const: zvfhmin
536 The standard Zvfhmin extension for vectored minimal half-precision
537 floating-point instructions, as ratified in commit e2ccd05
538 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
540 - const: zvkb
542 The standard Zvkb extension for vector cryptography bit-manipulation
544 riscv-crypto-spec-vector.adoc") of riscv-crypto.
546 - const: zvkg
548 The standard Zvkg extension for vector GCM/GMAC instructions, as
549 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
550 of riscv-crypto.
552 - const: zvkn
554 The standard Zvkn extension for NIST algorithm suite instructions, as
555 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
556 of riscv-crypto.
558 - const: zvknc
560 The standard Zvknc extension for NIST algorithm suite with carryless
562 riscv-crypto-spec-vector.adoc") of riscv-crypto.
564 - const: zvkned
566 The standard Zvkned extension for Vector AES block cipher
568 riscv-crypto-spec-vector.adoc") of riscv-crypto.
570 - const: zvkng
572 The standard Zvkng extension for NIST algorithm suite with GCM
574 riscv-crypto-spec-vector.adoc") of riscv-crypto.
576 - const: zvknha
578 The standard Zvknha extension for NIST suite: vector SHA-2 secure,
579 hash (SHA-256 only) instructions, as ratified in commit
580 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
582 - const: zvknhb
584 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
585 hash (SHA-256 and SHA-512) instructions, as ratified in commit
586 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
588 - const: zvks
590 The standard Zvks extension for ShangMi algorithm suite
592 riscv-crypto-spec-vector.adoc") of riscv-crypto.
594 - const: zvksc
596 The standard Zvksc extension for ShangMi algorithm suite with
598 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
600 - const: zvksed
602 The standard Zvksed extension for ShangMi suite: SM4 block cipher
604 riscv-crypto-spec-vector.adoc") of riscv-crypto.
606 - const: zvksh
608 The standard Zvksh extension for ShangMi suite: SM3 secure hash
610 riscv-crypto-spec-vector.adoc") of riscv-crypto.
612 - const: zvksg
614 The standard Zvksg extension for ShangMi algorithm suite with GCM
616 riscv-crypto-spec-vector.adoc") of riscv-crypto.
618 - const: zvkt
620 The standard Zvkt extension for vector data-independent execution
622 riscv-crypto-spec-vector.adoc") of riscv-crypto.
624 - const: xandespmu
626 The Andes Technology performance monitor extension for counter overflow
629 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
633 - if:
640 - if:
645 - contains:
647 - contains:
650 - if:
655 - contains:
657 - contains:
660 - if:
668 # Zcf extension does not exist on rv64
669 - if:
671 riscv,isa-extensions:
674 riscv,isa-base:
679 riscv,isa-extensions: