Lines Matching +full:riscv +full:- +full:crypto +full:- +full:spec +full:- +full:vector
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
31 const: riscv
34 riscv,isa:
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from
39 https://riscv.org/specifications/
43 Notably, riscv,isa was defined prior to the creation of the
48 insensitive, letters in the riscv,isa string must be all
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
54 riscv,isa-base:
59 - rv32i
60 - rv64i
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/string-array
69 - const: i
78 - const: m
84 - const: a
89 - const: f
91 The standard F extension for single-precision floating point, as
95 - const: d
97 The standard D extension for double-precision floating-point, as
101 - const: q
103 The standard Q extension for quad-precision floating-point, as
107 - const: c
112 - const: v
114 The standard V extension for vector operations, as ratified
115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec.
118 - const: h
123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia
126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine-mode-visible csr and behavioural
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
131 - const: smmpm
133 The standard Smmpm extension for M-mode pointer masking as
135 of riscv-j-extension.
137 - const: smnpm
139 The standard Smnpm extension for next-mode pointer masking as
141 of riscv-j-extension.
143 - const: smstateen
146 added by other RISC-V extensions in H/S/VS/U/VU modes and as
147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
149 - const: ssaia
151 The standard Ssaia supervisor-level extension for the advanced
152 interrupt architecture for supervisor-mode-visible csr and
154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
156 - const: sscofpmf
158 The standard Sscofpmf supervisor-level extension for count overflow
159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
160 to manually trigger workflow. (#2)") of riscv-count-overflow.
162 - const: ssnpm
164 The standard Ssnpm extension for next-mode pointer masking as
166 of riscv-j-extension.
168 - const: sstc
170 The standard Sstc supervisor-level extension for time compare as
172 workflow. (#2)") of riscv-time-compare.
174 - const: svade
176 The standard Svade supervisor-level extension for SW-managed PTE A/D
192 Svadu turned-off at boot time. To use Svadu, supervisor must
195 - const: svadu
197 The standard Svadu supervisor-level extension for hardware updating
199 privileged ISA specification. Please refer to Svade dt-binding
202 - const: svinval
204 The standard Svinval supervisor-level extension for fine-grained
205 address-translation cache invalidation as ratified in the 20191213
208 - const: svnapot
210 The standard Svnapot supervisor-level extensions for napot
214 - const: svpbmt
216 The standard Svpbmt supervisor-level extensions for page-based
220 - const: svrsw60t59b
224 for SW bits 60:59") of riscv-non-isa/riscv-iommu.
226 - const: svvptc
228 The standard Svvptc supervisor-level extension for
229 address-translation cache behaviour with respect to invalid entries
231 riscv-svvptc.
233 - const: zaamo
239 - const: zabha
243 riscv-zabha.
245 - const: zacas
247 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
249 ratified") of the riscv-zacas.
251 - const: zalasr
253 The standard Zalasr extension for load-acquire/store-release as frozen
254 at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
256 - const: zalrsc
258 The standard Zalrsc extension for load-reserved/store-conditional as
262 - const: zawrs
264 The Zawrs extension for entering a low-power state or for trapping
267 riscv/zawrs") of riscv-isa-manual.
269 - const: zba
271 The standard Zba bit-manipulation extension for address generation
273 request #158 from hirooih/clmul-fix-loop-end-condition") of
274 riscv-bitmanip.
276 - const: zbb
278 The standard Zbb bit-manipulation extension for basic bit-manipulation
280 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
282 - const: zbc
284 The standard Zbc bit-manipulation extension for carry-less
286 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
288 - const: zbkb
291 in version 1.0 of RISC-V Cryptography Extensions Volume I
294 - const: zbkc
296 The standard Zbkc carry-less multiply instructions as ratified
297 in version 1.0 of RISC-V Cryptography Extensions Volume I
300 - const: zbkx
303 in version 1.0 of RISC-V Cryptography Extensions Volume I
306 - const: zbs
308 The standard Zbs bit-manipulation extension for single-bit
310 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
312 - const: zca
316 RV64 as it contains no instructions") of riscv-code-size-reduction,
317 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
320 - const: zcb
324 RV64 as it contains no instructions") of riscv-code-size-reduction,
325 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
328 - const: zcd
332 RV64 as it contains no instructions") of riscv-code-size-reduction,
333 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
336 - const: zcf
340 RV64 as it contains no instructions") of riscv-code-size-reduction,
341 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
344 - const: zcmop
347 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
349 - const: zfa
353 riscv-isa-manual.
355 - const: zfbfmin
358 16-bit half-precision brain floating-point instructions, as ratified
359 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
361 - const: zfh
363 The standard Zfh extension for 16-bit half-precision binary
364 floating-point instructions, as ratified in commit 64074bc ("Update
365 version numbers for Zfh/Zfinx") of riscv-isa-manual.
367 - const: zfhmin
370 16-bit half-precision binary floating-point instructions, as ratified
372 riscv-isa-manual.
374 - const: ziccrse
378 ("Updated to ratified state.") of the riscv profiles specification.
380 - const: zk
383 in version 1.0 of RISC-V Cryptography Extensions Volume I
386 - const: zkn
389 version 1.0 of RISC-V Cryptography Extensions Volume I
392 - const: zknd
395 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
398 - const: zkne
401 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
404 - const: zknh
407 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
410 - const: zkr
413 1.0 of RISC-V Cryptography Extensions Volume I specification.
416 device-tree has been provided.
418 - const: zks
421 version 1.0 of RISC-V Cryptography Extensions Volume I
424 - const: zksed
427 as ratified in version 1.0 of RISC-V Cryptography Extensions
430 - const: zksh
433 as ratified in version 1.0 of RISC-V Cryptography Extensions
436 - const: zkt
439 in version 1.0 of RISC-V Cryptography Extensions Volume I
442 - const: zicbom
445 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
447 - const: zicbop
449 The standard Zicbop extension for cache-block prefetch instructions
450 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
451 riscv-CMOs.
453 - const: zicboz
455 The standard Zicboz extension for cache-block zeroing as ratified
456 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
458 - const: zicntr
464 - const: zicond
467 conditional-select/move operations as ratified in commit 95cf1f9
468 ("Add changes requested by Ved during signoff") of riscv-zicond.
470 - const: zicsr
477 special case read-only CSRs, that were moved into the Zicntr and
481 - const: zifencei
483 The standard Zifencei extension for instruction-fetch fence, as
487 - const: zihintpause
490 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
492 - const: zihintntl
494 The standard Zihintntl extension for non-temporal locality hints, as
496 riscv-isa-manual.
498 - const: zihpm
504 - const: zimop
507 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
509 - const: ztso
513 riscv-isa-manual.
515 - const: zvbb
517 The standard Zvbb extension for vectored basic bit-manipulation
519 riscv-crypto-spec-vector.adoc") of riscv-crypto.
521 - const: zvbc
525 riscv-crypto-spec-vector.adoc") of riscv-crypto.
527 - const: zve32f
530 in commit 6f702a2 ("Vector extensions are now ratified") of
531 riscv-v-spec.
533 - const: zve32x
536 in commit 6f702a2 ("Vector extensions are now ratified") of
537 riscv-v-spec.
539 - const: zve64d
542 in commit 6f702a2 ("Vector extensions are now ratified") of
543 riscv-v-spec.
545 - const: zve64f
548 in commit 6f702a2 ("Vector extensions are now ratified") of
549 riscv-v-spec.
551 - const: zve64x
554 in commit 6f702a2 ("Vector extensions are now ratified") of
555 riscv-v-spec.
557 - const: zvfbfmin
560 16-bit half-precision brain floating-point instructions, as ratified
561 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
563 - const: zvfbfwma
565 The standard Zvfbfwma extension for vectored half-precision brain
566 floating-point widening multiply-accumulate instructions, as ratified
567 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
569 - const: zvfh
571 The standard Zvfh extension for vectored half-precision
572 floating-point instructions, as ratified in commit e2ccd05
573 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
575 - const: zvfhmin
577 The standard Zvfhmin extension for vectored minimal half-precision
578 floating-point instructions, as ratified in commit e2ccd05
579 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
581 - const: zvkb
583 The standard Zvkb extension for vector cryptography bit-manipulation
585 riscv-crypto-spec-vector.adoc") of riscv-crypto.
587 - const: zvkg
589 The standard Zvkg extension for vector GCM/GMAC instructions, as
590 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
591 of riscv-crypto.
593 - const: zvkn
596 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
597 of riscv-crypto.
599 - const: zvknc
603 riscv-crypto-spec-vector.adoc") of riscv-crypto.
605 - const: zvkned
607 The standard Zvkned extension for Vector AES block cipher
609 riscv-crypto-spec-vector.adoc") of riscv-crypto.
611 - const: zvkng
615 riscv-crypto-spec-vector.adoc") of riscv-crypto.
617 - const: zvknha
619 The standard Zvknha extension for NIST suite: vector SHA-2 secure,
620 hash (SHA-256 only) instructions, as ratified in commit
621 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
623 - const: zvknhb
625 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
626 hash (SHA-256 and SHA-512) instructions, as ratified in commit
627 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
629 - const: zvks
633 riscv-crypto-spec-vector.adoc") of riscv-crypto.
635 - const: zvksc
639 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
641 - const: zvksed
645 riscv-crypto-spec-vector.adoc") of riscv-crypto.
647 - const: zvksh
651 riscv-crypto-spec-vector.adoc") of riscv-crypto.
653 - const: zvksg
657 riscv-crypto-spec-vector.adoc") of riscv-crypto.
659 - const: zvkt
661 The standard Zvkt extension for vector data-independent execution
663 riscv-crypto-spec-vector.adoc") of riscv-crypto.
669 - const: xandespmu
674 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
677 - const: xmipsexectl
680 …https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.p…
683 - const: xsfcease
687 https://www.sifive.com/document-file/freedom-u740-c000-manual
689 - const: xsfcflushdlone
693 https://www.sifive.com/document-file/freedom-u740-c000-manual
695 - const: xsfpgflushdlone
701 - const: xsfvqmaccdod
705 … https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
707 - const: xsfvqmaccqoq
711 … https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
713 - const: xsfvfnrclipxfqf
715 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.
717 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
719 - const: xsfvfwmaccqqq
723 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction
725 # T-HEAD
726 - const: xtheadvector
728 The T-HEAD specific 0.7.1 vector implementation as written in
729 …https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/…
732 - if:
739 - if:
746 - if:
751 - contains:
753 - contains:
756 - if:
761 - contains:
763 - contains:
766 - if:
773 - if:
780 - if:
785 - contains:
787 - contains:
790 - if:
795 - contains:
797 - contains:
800 - if:
807 - if:
814 - if:
819 - contains:
821 - contains:
824 - if:
831 - if:
836 - contains:
838 - contains:
840 - contains:
843 - if:
848 - contains:
850 - contains:
853 - if:
856 - const: zvbc
857 - const: zvkn
858 - const: zvknc
859 - const: zvkng
860 - const: zvknhb
861 - const: zvksc
865 - const: v
866 - const: zve64x
868 - if:
871 - const: zvbb
872 - const: zvkb
873 - const: zvkg
874 - const: zvkned
875 - const: zvknha
876 - const: zvksed
877 - const: zvksh
878 - const: zvks
879 - const: zvkt
883 - const: v
884 - const: zve32x
888 - if:
890 riscv,isa-extensions:
893 riscv,isa-base:
898 riscv,isa-extensions: