Lines Matching full:extensions

4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
7 title: RISC-V ISA extensions
15   RISC-V has a large number of extensions, some of which are "standard"
16   extensions, meaning they are ratified by RISC-V International, and others
17   are "vendor" extensions.
23   The properties for standard extensions therefore map to their originally
24   ratified states, with the exception of the I, Zicntr & Zihpm extensions.
44       Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
62   riscv,isa-extensions:
65     description: Extensions supported by the hart.
68         # single letter extensions, in canonical order
75             the Zicntr and Zihpm extensions after the ratification of the
123         # multi-letter extensions, sorted alphanumerically
146             added by other RISC-V extensions in H/S/VS/U/VU modes and as
180             Both Svade and Svadu extensions control the hardware behavior when
182             possible combinations of these extensions in the device tree are:
210             The standard Svnapot supervisor-level extensions for napot
216             The standard Svpbmt supervisor-level extensions for page-based
291             in version 1.0 of RISC-V Cryptography Extensions Volume I
297             in version 1.0 of RISC-V Cryptography Extensions Volume I
303             in version 1.0 of RISC-V Cryptography Extensions Volume I
314             The Zca extension part of Zc* standard extensions for code size
322             The Zcb extension part of Zc* standard extensions for code size
330             The Zcd extension part of Zc* standard extensions for code size
338             The Zcf extension part of Zc* standard extensions for code size
383             in version 1.0 of RISC-V Cryptography Extensions Volume I
388             The standard Zkn NIST algorithm suite extensions as ratified in
389             version 1.0 of RISC-V Cryptography Extensions Volume I
395             ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
401             ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
407             ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
413             1.0 of RISC-V Cryptography Extensions Volume I specification.
420             The standard Zks ShangMi algorithm suite extensions as ratified in
421             version 1.0 of RISC-V Cryptography Extensions Volume I
427             as ratified in version 1.0 of RISC-V Cryptography Extensions
433             as ratified in version 1.0 of RISC-V Cryptography Extensions
439             in version 1.0 of RISC-V Cryptography Extensions Volume I
478             Zihpm extensions after the ratification of the 20191213 version of
530             in commit 6f702a2 ("Vector extensions are now ratified") of
536             in commit 6f702a2 ("Vector extensions are now ratified") of
542             in commit 6f702a2 ("Vector extensions are now ratified") of
548             in commit 6f702a2 ("Vector extensions are now ratified") of
554             in commit 6f702a2 ("Vector extensions are now ratified") of
665         # vendor extensions, each extension sorted alphanumerically under the
685             SiFive CEASE Instruction Extensions Specification.
691             SiFive L1D Cache Flush Instruction Extensions Specification.
697             SiFive PGFLUSH Instruction Extensions for the power management. The
703             SiFive Int8 Matrix Multiplication Extensions Specification.
705 …    https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
709             SiFive Int8 Matrix Multiplication Extensions Specification.
711 …    https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
715             SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.
721             SiFive Matrix Multiply Accumulate Instruction Extensions Specification.
890         riscv,isa-extensions:
898         riscv,isa-extensions: