Lines Matching +full:system +full:- +full:cache +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml
29 - if:
35 - thead,c906
36 - thead,c910
37 - thead,c920
45 - items:
46 - enum:
47 - amd,mbv32
48 - amd,mbv64
49 - andestech,ax45mp
50 - canaan,k210
51 - sifive,bullet0
52 - sifive,e5
53 - sifive,e7
54 - sifive,e71
55 - sifive,rocket0
56 - sifive,s7
57 - sifive,u5
58 - sifive,u54
59 - sifive,u7
60 - sifive,u74
61 - sifive,u74-mc
62 - spacemit,x60
63 - thead,c906
64 - thead,c908
65 - thead,c910
66 - thead,c920
67 - const: riscv
68 - items:
69 - enum:
70 - sifive,e51
71 - sifive,u54-mc
72 - const: sifive,rocket0
73 - const: riscv
74 - const: riscv # Simulator only
76 Identifies that the hart uses the RISC-V instruction set
79 mmu-type:
82 this hart. These values originate from the RISC-V Privileged
87 - riscv,sv32
88 - riscv,sv39
89 - riscv,sv48
90 - riscv,sv57
91 - riscv,none
97 riscv,cbom-block-size:
100 The blocksize in bytes for the Zicbom cache operations.
102 riscv,cbop-block-size:
105 The blocksize in bytes for the Zicbop cache operations.
107 riscv,cboz-block-size:
110 The blocksize in bytes for the Zicboz cache operations.
119 # RISC-V has multiple properties for cache op block sizes as the sizes
121 cache-op-block-size: false
122 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
123 timebase-frequency: false
125 interrupt-controller:
127 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
129 cpu-idle-states:
130 $ref: /schemas/types.yaml#/definitions/phandle-array
135 by this hart (see ./idle-states.yaml).
137 capacity-dmips-mhz:
139 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
140 DMIPS/MHz, relative to highest capacity-dmips-mhz
141 in the system.
144 - required:
145 - riscv,isa
146 - required:
147 - riscv,isa-base
150 riscv,isa-base: [ "riscv,isa-extensions" ]
151 riscv,isa-extensions: [ "riscv,isa-base" ]
154 - interrupt-controller
159 - |
162 #address-cells = <1>;
163 #size-cells = <0>;
164 timebase-frequency = <1000000>;
166 clock-frequency = <0>;
169 i-cache-block-size = <64>;
170 i-cache-sets = <128>;
171 i-cache-size = <16384>;
173 riscv,isa-base = "rv64i";
174 riscv,isa-extensions = "i", "m", "a", "c";
176 cpu_intc0: interrupt-controller {
177 #interrupt-cells = <1>;
178 compatible = "riscv,cpu-intc";
179 interrupt-controller;
183 clock-frequency = <0>;
185 d-cache-block-size = <64>;
186 d-cache-sets = <64>;
187 d-cache-size = <32768>;
188 d-tlb-sets = <1>;
189 d-tlb-size = <32>;
191 i-cache-block-size = <64>;
192 i-cache-sets = <64>;
193 i-cache-size = <32768>;
194 i-tlb-sets = <1>;
195 i-tlb-size = <32>;
196 mmu-type = "riscv,sv39";
198 tlb-split;
199 riscv,isa-base = "rv64i";
200 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
202 cpu_intc1: interrupt-controller {
203 #interrupt-cells = <1>;
204 compatible = "riscv,cpu-intc";
205 interrupt-controller;
210 - |
213 #address-cells = <1>;
214 #size-cells = <0>;
219 mmu-type = "riscv,sv48";
220 riscv,isa-base = "rv64i";
221 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
223 interrupt-controller {
224 #interrupt-cells = <1>;
225 interrupt-controller;
226 compatible = "riscv,cpu-intc";