Lines Matching +full:idle +full:- +full:state
1 IBM Power-Management Bindings
5 idle states. The description of these idle states is exposed via the
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
10 Typically each idle state has the following associated properties:
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
16 idle states and so on. The flag bits are as follows:
18 - exit-latency: The latency involved in transitioning the state of the
19 CPU from idle to running.
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
26 ----------------
27 The following properties provide details about the idle states. These
29 provides the value of that property for the idle state associated with
32 If idle-states are defined, then the properties
33 "ibm,cpu-idle-state-names" and "ibm,cpu-idle-state-flags" are
37 - ibm,cpu-idle-state-names:
38 Array of strings containing the names of the idle states.
40 - ibm,cpu-idle-state-flags:
41 Array of unsigned 32-bit values containing the values of the
42 flags associated with the aforementioned idle-states. The
49 0x00010000 /* This is a nap state (POWER7,POWER8) */
50 0x00020000 /* This is a fast-sleep state (POWER8)*/
51 0x00040000 /* This is a winkle state (POWER8) */
52 0x00080000 /* This is a fast-sleep state which requires a */
55 0x00800000 /* This state uses SPR PMICR instruction */
57 0x00100000 /* This is a fast stop state (POWER9) */
58 0x00200000 /* This is a deep-stop state (POWER9) */
60 - ibm,cpu-idle-state-latencies-ns:
61 Array of unsigned 32-bit values containing the values of the
62 exit-latencies (in ns) for the idle states in
63 ibm,cpu-idle-state-names.
65 - ibm,cpu-idle-state-residency-ns:
66 Array of unsigned 32-bit values containing the values of the
67 target-residency (in ns) for the idle states in
68 ibm,cpu-idle-state-names. On POWER8 this is an optional
73 - ibm,cpu-idle-state-psscr:
74 Array of unsigned 64-bit values containing the values for the
75 PSSCR for each of the idle states in ibm,cpu-idle-state-names.
78 - ibm,cpu-idle-state-psscr-mask:
79 Array of unsigned 64-bit values containing the masks
81 entries of ibm,cpu-idle-state-psscr. This property is
85 ibm,cpu-idle-state-psscr-mask value to 0xf, it implies that
87 in ibm,cpu-idle-state-psscr should be considered by the
88 kernel. For such idle states, the kernel would set the
89 remaining fields of the psscr to the following sane-default
92 - ESL and EC bits are to 1. So wakeup from any stop
93 state will be at vector 0x100.
95 - MTL and PSLL are set to the maximum allowed value as
98 - The Transition Rate, TR is set to the Maximum value
102 ibm,cpu-idle-state-psscr-mask, the kernel expects all the
104 ibm,cpu-idle-state-psscr to be correctly set by the firmware.
106 - ibm,cpu-idle-state-pmicr:
107 Array of unsigned 64-bit values containing the pmicr values
108 for the idle states in ibm,cpu-idle-state-names. This 64-bit
110 state if the flag indicates that pmicr SPR should be set. This
114 - ibm,cpu-idle-state-pmicr-mask:
115 Array of unsigned 64-bit values containing the mask indicating
117 entries in ibm,cpu-idle-state-pmicr. This is an optional