Lines Matching full:mpic

2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
17       Definition: Shall include "fsl,mpic".  Freescale MPIC
20           0x10 in the MPIC.
51           MPIC must not be reset by the client program, and that
63           If present the MPIC will be assumed to be big-endian.  Some
64           device-trees omit this property on MPIC nodes even when the MPIC is
70           If present the MPIC will be assumed to only be able to route
71           non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
112                       MPIC a block of registers referred to as
127                   2 = MPIC inter-processor interrupt (IPI)
130                       the MPIC IPI number.  The type-specific
133                   3 = MPIC timer interrupt
136                       the MPIC timer number.  The type-specific
150 	 * mpic interrupt controller with 4 cells per specifier
152 	mpic: pic@40000 {
153 		compatible = "fsl,mpic";
185 		interrupt-parent = <&mpic>;
193 	 *  MPIC IPI interrupts.  Note the interrupt
197 		compatible = "fsl,mpic-ipi";
207 	 *  Definition of a node defining the MPIC
212 		compatible = "fsl,mpic-global-timer";