Lines Matching +full:power +full:-

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC PMGR Power States
10   - Hector Martin <marcan@marcan.st>
13   - $ref: power-domain.yaml#
16   Apple SoCs include PMGR blocks responsible for power management,
17   which can control various clocks, resets, power states, and
18   performance features. This binding describes the device power
19   state registers, which control power states and resets.
21   Each instance of a power controller within the PMGR syscon node
22   represents a generic power domain provider, as documented in
23   Documentation/devicetree/bindings/power/power-domain.yaml.
24   The provider controls a single SoC block. The power hierarchy is
25   represented via power-domains relationships between these nodes.
28   for the top-level PMGR node documentation.
33       - enum:
34           - apple,t8103-pmgr-pwrstate
35           - apple,t8112-pmgr-pwrstate
36           - apple,t6000-pmgr-pwrstate
37       - const: apple,pmgr-pwrstate
42   "#power-domain-cells":
45   "#reset-cells":
48   power-domains:
50       Reference to parent power domains. A domain may have multiple parents,
58       name the power/reset domains.
60   apple,always-on:
62       Forces this power domain to always be powered up.
65   apple,min-state:
67       Specifies the minimum power state for auto-PM.
68       0 = power gated, 4 = clock gated, 15 = on.
74   - compatible
75   - reg
76   - "#power-domain-cells"
77   - "#reset-cells"
78   - label