Lines Matching +full:zynq +full:- +full:can +full:- +full:1

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Pinctrl
10   - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13   Please refer to pinctrl-bindings.txt in this directory for details of the
17   Zynq's pin configuration nodes act as a container for an arbitrary number of
19   pin, a group, or a list of pins or groups. This configuration can include the
21   parameters, such as pull-up, slew rate, etc.
23   Each configuration node can consist of multiple nodes describing the pinmux and
24   pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
31     const: xlnx,pinctrl-zynq
35     maxItems: 1
42   '^(.*-)?(default|gpio-grp)$':
50         $ref: pinmux-node.yaml#
120           - groups
121           - function
130         $ref: pincfg-node.yaml#
141               pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
144           bias-pull-up: true
146           bias-pull-down: true
148           bias-disable: true
150           bias-high-impedance: true
152           low-power-enable: true
154           low-power-disable: true
156           slew-rate:
157             enum: [0, 1]
159           power-source:
160             enum: [1, 2, 3, 4]
163           - required: [ groups ]
164           - required: [ pins ]
171   - $ref: pinctrl.yaml#
174   - compatible
175   - reg
176   - syscon
181   - |
182     #include <dt-bindings/pinctrl/pinctrl-zynq.h>
184        compatible = "xlnx,pinctrl-zynq";
188        pinctrl_uart1_default: uart1-default {
196                slew-rate = <0>;
197                power-source = <IO_STANDARD_LVCMOS18>;
200            conf-rx {
202                bias-high-impedance;
205            conf-tx {
207                bias-disable;
213          pinctrl-names = "default";
214          pinctrl-0 = <&pinctrl_uart1_default>;