Lines Matching +full:bias +full:- +full:pull +full:- +full:pin +full:- +full:default
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
15 phrase "pin configuration node".
17 Zynq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those pin(s)/group(s), and various pin configuration
21 parameters, such as pull-up, slew rate, etc.
31 const: xlnx,pinctrl-zynq
42 '^(.*-)?(default|gpio-grp)$':
48 Pinctrl node's client devices use subnodes for pin muxes,
50 $ref: pinmux-node.yaml#
111 given pin groups.
120 - groups
121 - function
128 Pinctrl node's client devices use subnodes for pin configurations,
130 $ref: pincfg-node.yaml#
135 List of pin groups as mentioned above.
139 List of pin names to select in this subnode.
141 pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
144 bias-pull-up: true
146 bias-pull-down: true
148 bias-disable: true
150 bias-high-impedance: true
152 low-power-enable: true
154 low-power-disable: true
156 slew-rate:
159 power-source:
163 - required: [ groups ]
164 - required: [ pins ]
171 - $ref: pinctrl.yaml#
174 - compatible
175 - reg
176 - syscon
181 - |
182 #include <dt-bindings/pinctrl/pinctrl-zynq.h>
184 compatible = "xlnx,pinctrl-zynq";
188 pinctrl_uart1_default: uart1-default {
196 slew-rate = <0>;
197 power-source = <IO_STANDARD_LVCMOS18>;
200 conf-rx {
202 bias-high-impedance;
205 conf-tx {
207 bias-disable;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_uart1_default>;