Lines Matching +full:input +full:- +full:disable

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
21   - Jianlong Huang <jianlong.huang@starfivetech.com>
25     const: starfive,jh7110-sys-pinctrl
39   interrupt-controller: true
41   '#interrupt-cells':
44   gpio-controller: true
46   '#gpio-cells':
50   '-[0-9]+$':
54       '-pins$':
60           muxer configuration, bias, input enable/disable, input schmitt
61           trigger enable/disable, slew-rate and drive strength.
63           - $ref: /schemas/pinctrl/pincfg-node.yaml
64           - $ref: /schemas/pinctrl/pinmux-node.yaml
74           bias-disable: true
76           bias-pull-up:
79           bias-pull-down:
82           drive-strength:
85           input-enable: true
87           input-disable: true
89           input-schmitt-enable: true
91           input-schmitt-disable: true
93           slew-rate:
97   - compatible
98   - reg
99   - clocks
100   - interrupts
101   - interrupt-controller
102   - '#interrupt-cells'
103   - gpio-controller
104   - '#gpio-cells'
109   - |
111         compatible = "starfive,jh7110-sys-pinctrl";
116         interrupt-controller;
117         #interrupt-cells = <2>;
118         gpio-controller;
119         #gpio-cells = <2>;
121         uart0-0 {
122             tx-pins {
124                 bias-disable;
125                 drive-strength = <12>;
126                 input-disable;
127                 input-schmitt-disable;
128                 slew-rate = <0>;
131             rx-pins {
133                 bias-pull-up;
134                 drive-strength = <2>;
135                 input-enable;
136                 input-schmitt-enable;
137                 slew-rate = <0>;