Lines Matching +full:jh7110 +full:- +full:pwm
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 AON Pin Controller
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
15 Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
18 - Jianlong Huang <jianlong.huang@starfivetech.com>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
35 '#interrupt-cells':
38 gpio-controller: true
40 '#gpio-cells':
44 '-[0-9]+$':
48 '-pins$':
55 trigger enable/disable, slew-rate and drive strength.
57 - $ref: /schemas/pinctrl/pincfg-node.yaml
58 - $ref: /schemas/pinctrl/pinmux-node.yaml
67 bias-disable: true
69 bias-pull-up:
72 bias-pull-down:
75 drive-strength:
78 input-enable: true
80 input-disable: true
82 input-schmitt-enable: true
84 input-schmitt-disable: true
86 slew-rate:
90 - compatible
91 - reg
92 - interrupts
93 - interrupt-controller
94 - '#interrupt-cells'
95 - gpio-controller
96 - '#gpio-cells'
101 - |
103 compatible = "starfive,jh7110-aon-pinctrl";
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 gpio-controller;
110 #gpio-cells = <2>;
112 pwm-0 {
113 pwm-pins {
115 bias-disable;
116 drive-strength = <12>;
117 input-disable;
118 input-schmitt-disable;
119 slew-rate = <0>;