Lines Matching +full:px30 +full:- +full:pmu

1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Heiko Stuebner <heiko@sntech.de>
18   Please refer to pinctrl-bindings.txt in this directory for details of the
26   various pad settings such as pull-up, etc.
29   defined as gpio sub-nodes of the pinmux controller.
34       - rockchip,px30-pinctrl
35       - rockchip,rk2928-pinctrl
36       - rockchip,rk3036-pinctrl
37       - rockchip,rk3066a-pinctrl
38       - rockchip,rk3066b-pinctrl
39       - rockchip,rk3128-pinctrl
40       - rockchip,rk3188-pinctrl
41       - rockchip,rk3228-pinctrl
42       - rockchip,rk3288-pinctrl
43       - rockchip,rk3308-pinctrl
44       - rockchip,rk3328-pinctrl
45       - rockchip,rk3368-pinctrl
46       - rockchip,rk3399-pinctrl
47       - rockchip,rk3528-pinctrl
48       - rockchip,rk3562-pinctrl
49       - rockchip,rk3568-pinctrl
50       - rockchip,rk3576-pinctrl
51       - rockchip,rk3588-pinctrl
52       - rockchip,rv1108-pinctrl
53       - rockchip,rv1126-pinctrl
60   rockchip,pmu:
63       The phandle of the syscon node for the PMU registers,
68   "#address-cells":
71   "#size-cells":
77   - $ref: pinctrl.yaml#
80   - compatible
81   - rockchip,grf
84   "gpio@[0-9a-f]+$":
87     $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
92   "pcfg-[a-z0-9-]+$":
95       bias-disable: true
97       bias-pull-down: true
99       bias-pull-pin-default: true
101       bias-pull-up: true
103       drive-strength:
107       input-enable: true
109       input-schmitt-enable: true
111       output-high: true
113       output-low: true
125         $ref: /schemas/types.yaml#/definitions/uint32-matrix
129             - minimum: 0
133             - minimum: 0
137             - minimum: 0
142             - description:
144                 to use as described in pinctrl-bindings.txt.
147   - |
148     #include <dt-bindings/interrupt-controller/arm-gic.h>
149     #include <dt-bindings/pinctrl/rockchip.h>
152       compatible = "rockchip,rk3066a-pinctrl";
155       #address-cells = <1>;
156       #size-cells = <1>;
160         compatible = "rockchip,gpio-bank";
165         gpio-controller;
166         #gpio-cells = <2>;
168         interrupt-controller;
169         #interrupt-cells = <2>;
172       pcfg_pull_default: pcfg-pull-default {
173         bias-pull-pin-default;
177         uart2_xfer: uart2-xfer {
185       compatible = "snps,dw-apb-uart";
189       pinctrl-0 = <&uart2_xfer>;
190       pinctrl-names = "default";
191       reg-io-width = <1>;
192       reg-shift = <2>;