Lines Matching +full:qcs615 +full:- +full:tlmm
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. QCS615 TLMM block
10 - Lijuan Gao <quic_lijuang@quicinc.com>
13 Top Level Mode Multiplexer pin controller in Qualcomm QCS615 SoC.
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,qcs615-tlmm
25 reg-names:
27 - const: east
28 - const: west
29 - const: south
34 gpio-reserved-ranges:
38 gpio-line-names:
42 "-state$":
44 - $ref: "#/$defs/qcom-qcs615-tlmm-state"
45 - type: object
47 "-pins$":
48 $ref: "#/$defs/qcom-qcs615-tlmm-state"
52 qcom-qcs615-tlmm-state:
57 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
67 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$"
68 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
93 - pins
96 - compatible
97 - reg
98 - reg-names
103 - |
104 #include <dt-bindings/interrupt-controller/arm-gic.h>
106 tlmm: pinctrl@3000000 {
107 compatible = "qcom,qcs615-tlmm";
111 reg-names = "east", "west", "south";
113 gpio-ranges = <&tlmm 0 0 123>;
114 gpio-controller;
115 #gpio-cells = <2>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
119 qup3-uart2-state {