Lines Matching +full:tegra124 +full:- +full:pinmux

7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23   Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24   "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
28 - reset-names: Must include the following entries:
29   - padctl
30 - #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
31   See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.
34 ------------
36 Child nodes contain the pinmux configurations following the conventions from
37 the pinctrl-bindings.txt document. Typically a single, static configuration is
54 - nvidia,lanes: An array of strings. Each string is the name of a lane.
57 - nvidia,function: A string that is the name of the function (pad) that the
60 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
65   - otg-0, otg-1, otg-2:
71   - ulpi-0, hsic-0, hsic-1:
77   - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
86 -----------------
89 		compatible = "nvidia,tegra124-xusb-padctl";
92 		reset-names = "padctl";
94 		#phy-cells = <1>;
98 -------------------
100 	pcie-controller@1003000 {
104 		phy-names = "pcie";
112 		pinctrl-0 = <&padctl_default>;
113 		pinctrl-names = "default";
115 		padctl_default: pinmux {
117 				nvidia,lanes = "pcie-0", "pcie-1";
123 				nvidia,lanes = "pcie-2", "pcie-3",
124 					       "pcie-4";
130 				nvidia,lanes = "sata-0";