Lines Matching +full:sparx5 +full:- +full:sgpio
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
32 "#size-cells":
41 microchip,sgpio-port-ranges:
49 $ref: /schemas/types.yaml#/definitions/uint32-matrix
52 - description: |
56 - description: |
63 bus-frequency:
64 description: The sgpio controller frequency (Hz). This dictates
74 reset-names:
76 - const: switch
79 "^gpio@[0-1]$":
83 const: microchip,sparx5-sgpio-bank
91 gpio-controller: true
93 '#gpio-cells':
102 description: Specifies the sgpio IRQ (in parent controller)
105 interrupt-controller: true
107 '#interrupt-cells':
110 defined in include/dt-bindings/interrupt-controller/irq.h
120 - compatible
121 - reg
122 - gpio-controller
123 - '#gpio-cells'
124 - ngpios
131 - compatible
132 - reg
133 - clocks
134 - microchip,sgpio-port-ranges
135 - "#address-cells"
136 - "#size-cells"
139 - |
140 #include <dt-bindings/interrupt-controller/arm-gic.h>
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "microchip,sparx5-sgpio";
146 pinctrl-0 = <&sgpio2_pins>;
147 pinctrl-names = "default";
149 microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
150 bus-frequency = <25000000>;
153 compatible = "microchip,sparx5-sgpio-bank";
154 gpio-controller;
155 #gpio-cells = <3>;
158 interrupt-controller;
159 #interrupt-cells = <3>;
162 compatible = "microchip,sparx5-sgpio-bank";
164 gpio-controller;
165 #gpio-cells = <3>;