Lines Matching +full:multi +full:- +full:instance

6  - compatible: Should be one of
7  "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8  "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10  "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12  "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15  "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17  "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19  - reg : register ranges as listed in the reg-names property
20  - reg-names: "otghs_control" for control-phy-otghs
21 	      "power", "pcie_pcs" and "control_sma" for control-phy-pcie
24 omap_control_usb: omap-control-usb@4a002300 {
25         compatible = "ti,control-phy-otghs";
27         reg-names = "otghs_control";
33  - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
34    "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
35  - reg : Address and length of the register set for the device.
36  - reg-names: The names of the register addresses corresponding to the registers
38  - #phy-cells: determine the number of cells that should be given in the
40  - clocks: a list of phandles and clock-specifier pairs, one for each entry in
41    clock-names.
42  - clock-names: should include:
43    * "wkupclk" - wakeup clock.
44    * "sysclk" - system clock.
45    * "refclk" - reference clock.
46    * "dpll_ref" - external dpll ref clk
47    * "dpll_ref_m2" - external dpll ref clk
48    * "phy-div" - divider for apll
49    * "div-clk" - apll clock
52  - id: If there are multiple instance of the same type, in order to
53    differentiate between each instance "id" can be used (e.g., multi-lane PCIe
55  - syscon-pllreset: Handle to system control region that contains the
58  - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
62  - ctrl-module : phandle of the control module used by PHY driver to power on
66  - syscon-phy-power : phandle/offset pair. Phandle to the system control
72 	compatible = "ti,phy-usb3";
76 	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
77 	ctrl-module = <&omap_control_usb>;
78 	#phy-cells = <0>;
82 	clock-names =	"wkupclk",
88 	compatible = "ti,phy-pipe3-sata";
92 	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
93 	ctrl-module = <&omap_control_sata>;
95 	clock-names = "sysclk", "refclk";
96 	syscon-pllreset = <&scm_conf 0x3fc>;
97 	#phy-cells = <0>;