Lines Matching +full:cmn +full:- +full:refclk +full:- +full:dig +full:- +full:div
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
20 - ti,j7200-wiz-10g
21 - ti,j784s4-wiz-10g
23 power-domains:
29 description: clock-specifier to represent input to the WIZ
31 clock-names:
34 - const: fck
35 - const: core_ref_clk
36 - const: ext_ref_clk
37 - const: core_ref1_clk
39 num-lanes:
43 "#address-cells":
46 "#size-cells":
49 "#reset-cells":
52 "#clock-cells":
57 typec-dir-gpios:
60 GPIO to signal Type-C cable orientation for lane swap.
62 achieve the functionality of an external type-C plug flip mux.
64 typec-dir-debounce-ms:
69 Number of milliseconds to wait before sampling typec-dir-gpio.
71 Type-C spec states minimum CC pin debounce of 100 ms and maximum
74 refclk-dig:
89 "#clock-cells":
92 clock-output-names:
95 assigned-clocks:
98 assigned-clock-parents:
102 - clocks
103 - "#clock-cells"
104 - assigned-clocks
105 - assigned-clock-parents
113 "^pll[0|1]-refclk$":
125 "#clock-cells":
128 clock-output-names:
131 assigned-clocks:
134 assigned-clock-parents:
138 - clocks
139 - "#clock-cells"
140 - assigned-clocks
141 - assigned-clock-parents
143 "^cmn-refclk1?-dig-div$":
156 "#clock-cells":
159 clock-output-names:
163 - clocks
164 - "#clock-cells"
166 "^serdes@[0-9a-f]+$":
172 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
174 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
177 - compatible
178 - power-domains
179 - clocks
180 - clock-names
181 - num-lanes
182 - "#address-cells"
183 - "#size-cells"
184 - "#reset-cells"
185 - ranges
188 - if:
192 const: ti,j7200-wiz-10g
195 - ti,scm
200 - |
201 #include <dt-bindings/soc/ti,sci_pm_domain.h>
204 compatible = "ti,j721e-wiz-16g";
205 #address-cells = <1>;
206 #size-cells = <1>;
207 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
209 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
212 num-lanes = <2>;
213 #reset-cells = <1>;
216 pll0-refclk {
218 #clock-cells = <0>;
219 assigned-clocks = <&wiz1_pll0_refclk>;
220 assigned-clock-parents = <&k3_clks 293 13>;
223 pll1-refclk {
225 #clock-cells = <0>;
226 assigned-clocks = <&wiz1_pll1_refclk>;
227 assigned-clock-parents = <&k3_clks 293 0>;
230 cmn-refclk-dig-div {
232 #clock-cells = <0>;
235 cmn-refclk1-dig-div {
237 #clock-cells = <0>;
240 refclk-dig {
243 #clock-cells = <0>;
244 assigned-clocks = <&wiz0_refclk_dig>;
245 assigned-clock-parents = <&k3_clks 292 11>;
249 compatible = "ti,sierra-phy-t0";
250 reg-names = "serdes";
252 #address-cells = <1>;
253 #size-cells = <0>;
255 reset-names = "sierra_reset";
257 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";