Lines Matching +full:jh7110 +full:- +full:sys +full:- +full:syscon

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe 2.0 PHY
10   - Minda Chen <minda.chen@starfivetech.com>
14     const: starfive,jh7110-pcie-phy
19   "#phy-cells":
22   starfive,sys-syscon:
23     $ref: /schemas/types.yaml#/definitions/phandle-array
25       - items:
26           - description: phandle to System Register Controller sys_syscon node.
27           - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
29       The phandle to System Register Controller syscon node and the PHY connect offset
32   starfive,stg-syscon:
33     $ref: /schemas/types.yaml#/definitions/phandle-array
35       - items:
36           - description: phandle to System Register Controller stg_syscon node.
37           - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
38           - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
40       The phandle to System Register Controller syscon node and the offset
44   - compatible
45   - reg
46   - "#phy-cells"
51   - |
53         compatible = "starfive,jh7110-pcie-phy";
55         #phy-cells = <0>;
56         starfive,sys-syscon = <&sys_syscon 0x18>;
57         starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;